From patchwork Tue Nov 24 19:56:07 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 62554 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id nAOJuNIK013132 for ; Tue, 24 Nov 2009 19:56:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932388AbZKXT4J (ORCPT ); Tue, 24 Nov 2009 14:56:09 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1758101AbZKXT4J (ORCPT ); Tue, 24 Nov 2009 14:56:09 -0500 Received: from mail-pz0-f171.google.com ([209.85.222.171]:37493 "EHLO mail-pz0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757691AbZKXT4H (ORCPT ); Tue, 24 Nov 2009 14:56:07 -0500 Received: by pzk1 with SMTP id 1so5042432pzk.33 for ; Tue, 24 Nov 2009 11:56:13 -0800 (PST) Received: by 10.114.138.10 with SMTP id l10mr3630537wad.3.1259092573249; Tue, 24 Nov 2009 11:56:13 -0800 (PST) Received: from localhost ([216.254.16.51]) by mx.google.com with ESMTPS id 20sm3843620pzk.1.2009.11.24.11.56.12 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 24 Nov 2009 11:56:12 -0800 (PST) From: Kevin Hilman To: linux-omap@vger.kernel.org Subject: [PATCH 1/3] OMAP3: add omap_hwmods for UART1,2,3 Date: Tue, 24 Nov 2009 11:56:07 -0800 Message-Id: <1259092569-22352-2-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.6.5.1 In-Reply-To: <1259092569-22352-1-git-send-email-khilman@deeprootsystems.com> References: <1259092569-22352-1-git-send-email-khilman@deeprootsystems.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/omap_hwmod_34xx.h b/arch/arm/mach-omap2/omap_hwmod_34xx.h index b6076b9..8225bd3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_34xx.h +++ b/arch/arm/mach-omap2/omap_hwmod_34xx.h @@ -18,6 +18,7 @@ #include #include #include +#include #include "prm-regbits-34xx.h" @@ -48,6 +49,7 @@ static struct omap_hwmod_ocp_if omap34xx_mpu__l3 = { }; /* Slave interfaces on the L3 interconnect */ +/* KJH: OCP ifs which have L3 interconnect as the slave */ static struct omap_hwmod_ocp_if *omap34xx_l3_slaves[] = { &omap34xx_mpu__l3, }; @@ -69,6 +71,9 @@ static struct omap_hwmod omap34xx_l3_hwmod = { }; static struct omap_hwmod omap34xx_l4_wkup_hwmod; +static struct omap_hwmod omap34xx_uart1_hwmod; +static struct omap_hwmod omap34xx_uart2_hwmod; +static struct omap_hwmod omap34xx_uart3_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap34xx_l4_core__l4_wkup = { @@ -77,14 +82,75 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap34xx_uart1_addr_space[] = { + { + .pa_start = OMAP_UART1_BASE, + .pa_end = OMAP_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { + .master = &omap34xx_l4_core_hwmod, + .slave = &omap34xx_uart1_hwmod, + .clkdev_dev_id = NULL, + .clkdev_con_id = "uart1_ick", + .addr = omap34xx_uart1_addr_space, + .addr_cnt = ARRAY_SIZE(omap34xx_uart1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap34xx_uart2_addr_space[] = { + { + .pa_start = OMAP_UART2_BASE, + .pa_end = OMAP_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT |ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { + .master = &omap34xx_l4_core_hwmod, + .slave = &omap34xx_uart2_hwmod, + .clkdev_dev_id = NULL, + .clkdev_con_id = "uart2_ick", + .addr = omap34xx_uart2_addr_space, + .addr_cnt = ARRAY_SIZE(omap34xx_uart2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap34xx_uart3_addr_space[] = { + { + .pa_start = OMAP_UART3_BASE, + .pa_end = OMAP_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { + .master = &omap34xx_l4_per_hwmod, + .slave = &omap34xx_uart3_hwmod, + .clkdev_dev_id = NULL, + .clkdev_con_id = "uart3_ick", + .addr = omap34xx_uart3_addr_space, + .addr_cnt = ARRAY_SIZE(omap34xx_uart3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ +/* KJH: OCP ifs where L4 CORE is the slave */ static struct omap_hwmod_ocp_if *omap34xx_l4_core_slaves[] = { &omap34xx_l3__l4_core, }; /* Master interfaces on the L4_CORE interconnect */ +/* KJH: OCP ifs where L4 CORE is the master */ static struct omap_hwmod_ocp_if *omap34xx_l4_core_masters[] = { &omap34xx_l4_core__l4_wkup, + &omap3_l4_core__uart1, + &omap3_l4_core__uart2, }; /* L4 CORE */ @@ -104,6 +170,7 @@ static struct omap_hwmod_ocp_if *omap34xx_l4_per_slaves[] = { /* Master interfaces on the L4_PER interconnect */ static struct omap_hwmod_ocp_if *omap34xx_l4_per_masters[] = { + &omap3_l4_per__uart3, }; /* L4 PER */ @@ -136,6 +203,7 @@ static struct omap_hwmod omap34xx_l4_wkup_hwmod = { }; /* Master interfaces on the MPU device */ +/* KJH: OCP ifs where MPU is the master */ static struct omap_hwmod_ocp_if *omap34xx_mpu_masters[] = { &omap34xx_mpu__l3, }; @@ -150,12 +218,132 @@ static struct omap_hwmod omap34xx_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; +/* UART common */ + +static struct omap_hwmod_sysconfig uart_if_ctrl = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), +}; + +/* UART1 */ + +static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { + { .irq = INT_24XX_UART1_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart1_sdma_chs[] = { + { .name = "tx", .dma_ch = OMAP24XX_DMA_UART1_TX, }, + { .name = "rx", .dma_ch = OMAP24XX_DMA_UART1_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap34xx_uart1_slaves[] = { + &omap3_l4_core__uart1, +}; + +static struct omap_hwmod omap34xx_uart1_hwmod = { + .name = "uart1_hwmod", + .mpu_irqs = uart1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), + .sdma_chs = uart1_sdma_chs, + .sdma_chs_cnt = ARRAY_SIZE(uart1_sdma_chs), + .clkdev_dev_id = NULL, + .clkdev_con_id = "uart1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART1_SHIFT, + }, + }, + .slaves = omap34xx_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_uart1_slaves), + .sysconfig = &uart_if_ctrl, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART2 */ + +static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { + { .irq = INT_24XX_UART2_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart2_sdma_chs[] = { + { .name = "tx", .dma_ch = OMAP24XX_DMA_UART2_TX, }, + { .name = "rx", .dma_ch = OMAP24XX_DMA_UART2_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap34xx_uart2_slaves[] = { + &omap3_l4_core__uart2, +}; + +static struct omap_hwmod omap34xx_uart2_hwmod = { + .name = "uart2_hwmod", + .mpu_irqs = uart2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), + .sdma_chs = uart2_sdma_chs, + .sdma_chs_cnt = ARRAY_SIZE(uart2_sdma_chs), + .clkdev_dev_id = NULL, + .clkdev_con_id = "uart2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART2_SHIFT, + }, + }, + .slaves = omap34xx_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_uart2_slaves), + .sysconfig = &uart_if_ctrl, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART3 */ + +static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { + { .irq = INT_24XX_UART3_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart3_sdma_chs[] = { + { .name = "tx", .dma_ch = OMAP24XX_DMA_UART3_TX, }, + { .name = "rx", .dma_ch = OMAP24XX_DMA_UART3_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap34xx_uart3_slaves[] = { + &omap3_l4_per__uart3, +}; + +static struct omap_hwmod omap34xx_uart3_hwmod = { + .name = "uart3_hwmod", + .mpu_irqs = uart3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), + .sdma_chs = uart3_sdma_chs, + .sdma_chs_cnt = ARRAY_SIZE(uart3_sdma_chs), + .clkdev_dev_id = NULL, + .clkdev_con_id = "uart3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART3_SHIFT, + }, + }, + .slaves = omap34xx_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_uart3_slaves), + .sysconfig = &uart_if_ctrl, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + static __initdata struct omap_hwmod *omap34xx_hwmods[] = { &omap34xx_l3_hwmod, &omap34xx_l4_core_hwmod, &omap34xx_l4_per_hwmod, &omap34xx_l4_wkup_hwmod, &omap34xx_mpu_hwmod, + &omap34xx_uart1_hwmod, + &omap34xx_uart2_hwmod, + &omap34xx_uart3_hwmod, NULL, };