@@ -985,6 +985,9 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
if (pwrdm->banks < (bank + 1))
return -EEXIST;
+ if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
+ bank = 1;
+
/*
* The register bit names below may not correspond to the
* actual names of the bits in each powerdomain's register,
@@ -1032,6 +1035,9 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
if (pwrdm->banks < (bank + 1))
return -EEXIST;
+ if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
+ bank = 1;
+
/*
* The register bit names below may not correspond to the
* actual names of the bits in each powerdomain's register,
@@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = {
.wkdep_srcs = mpu_34xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .flags = PWRDM_HAS_MPU_QUIRK,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET,
@@ -40,7 +40,10 @@
/* Powerdomain flags */
#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
-
+#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
+ * in MEM bank 1 position. This is
+ * true for OMAP3430
+ */
/*
* Number of memory banks that are power-controllable. On OMAP3430, the