From patchwork Mon Jan 18 08:29:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripathy, Vishwanath" X-Patchwork-Id: 73636 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id o0I8QDV3005675 for ; Mon, 18 Jan 2010 08:26:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752920Ab0ARI0M (ORCPT ); Mon, 18 Jan 2010 03:26:12 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751598Ab0ARI0L (ORCPT ); Mon, 18 Jan 2010 03:26:11 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:55819 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932105Ab0ARI0H (ORCPT ); Mon, 18 Jan 2010 03:26:07 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o0I8PxYl000927 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 18 Jan 2010 02:26:01 -0600 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o0I8PusL015522; Mon, 18 Jan 2010 13:55:58 +0530 (IST) From: Vishwanath BS To: linux-omap@vger.kernel.org Cc: Vishwanath BS , Paul Walmsley , Vishwanath BS Subject: [PATCHV5 4/4] OMAP3: add support for 192Mhz DPLL4M2 output Date: Mon, 18 Jan 2010 13:59:22 +0530 Message-Id: <1263803362-7083-5-git-send-email-vishwanath.bs@ti.com> X-Mailer: git-send-email 1.5.6.3 In-Reply-To: <1263803362-7083-4-git-send-email-vishwanath.bs@ti.com> References: <1263803362-7083-1-git-send-email-vishwanath.bs@ti.com> <1263803362-7083-2-git-send-email-vishwanath.bs@ti.com> <1263803362-7083-3-git-send-email-vishwanath.bs@ti.com> <1263803362-7083-4-git-send-email-vishwanath.bs@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index a9ec184..1a21a91 100755 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -692,18 +692,24 @@ static struct clk dpll4_m2x2_ck = { * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and * CM_96K_(F)CLK. */ -static struct clk omap_96m_alwon_fck = { - .name = "omap_96m_alwon_fck", - .ops = &clkops_null, - .parent = &dpll4_m2x2_ck, - .recalc = &followparent_recalc, + +/* Adding 192MHz Clock node needed by SGX */ +static struct clk omap_192_alwon_fck = { + .name = "omap_192_alwon_fck", + .ops = &clkops_null, + .parent = &dpll4_m2x2_ck, + .recalc = &followparent_recalc, }; -static struct clk cm_96m_fck = { - .name = "cm_96m_fck", - .ops = &clkops_null, - .parent = &omap_96m_alwon_fck, - .recalc = &followparent_recalc, +static const struct clksel_rate omap_96m_alwon_fck_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_36XX }, + { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel omap_96m_alwon_fck_clksel[] = { + { .parent = &omap_192_alwon_fck, .rates = omap_96m_alwon_fck_rates }, + { .parent = NULL } }; static const struct clksel_rate omap_96m_dpll_rates[] = { @@ -716,6 +722,31 @@ static const struct clksel_rate omap_96m_sys_rates[] = { { .div = 0 } }; +static struct clk omap_96m_alwon_fck = { + .name = "omap_96m_alwon_fck", + .ops = &clkops_null, + .parent = &dpll4_m2x2_ck, + .recalc = &followparent_recalc, +}; + +static struct clk omap_96m_alwon_fck_3630 = { + .name = "omap_96m_alwon_fck", + .parent = &omap_192_alwon_fck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3630_CLKSEL_96M_MASK, + .clksel = omap_96m_alwon_fck_clksel +}; + +static struct clk cm_96m_fck = { + .name = "cm_96m_fck", + .ops = &clkops_null, + .parent = &omap_96m_alwon_fck, + .recalc = &followparent_recalc, +}; + static const struct clksel omap_96m_fck_clksel[] = { { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, { .parent = &sys_ck, .rates = omap_96m_sys_rates }, @@ -1308,12 +1339,24 @@ static struct clk gfx_cg2_ck = { /* SGX power domain - 3430ES2 only */ static const struct clksel_rate sgx_core_rates[] = { + { .div = 2, .val = 5, .flags = RATE_IN_36XX }, { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, { .div = 4, .val = 1, .flags = RATE_IN_343X }, { .div = 6, .val = 2, .flags = RATE_IN_343X }, { .div = 0 }, }; +static const struct clksel_rate sgx_192m_rates[] = { + { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel_rate sgx_corex2_rates[] = { + { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE }, + { .div = 5, .val = 7, .flags = RATE_IN_36XX }, + { .div = 0 }, +}; + static const struct clksel_rate sgx_96m_rates[] = { { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, { .div = 0 }, @@ -1322,7 +1365,9 @@ static const struct clksel_rate sgx_96m_rates[] = { static const struct clksel sgx_clksel[] = { { .parent = &core_ck, .rates = sgx_core_rates }, { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, - { .parent = NULL }, + { .parent = &omap_192_alwon_fck, .rates = sgx_192m_rates }, + { .parent = &corex2_fck, .rates = sgx_corex2_rates }, + { .parent = NULL } }; static struct clk sgx_fck = { @@ -1336,6 +1381,8 @@ static struct clk sgx_fck = { .clksel = sgx_clksel, .clkdm_name = "sgx_clkdm", .recalc = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate }; static struct clk sgx_ick = { @@ -3159,6 +3206,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), + CLK(NULL, "omap_192_alwon_fck", &omap_192_alwon_fck, CK_36XX), CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), @@ -3401,6 +3449,8 @@ int __init omap2_clk_init(void) dpll4_m5_ck = dpll4_m5_ck_34xx; dpll4_m6_ck = dpll4_m6_ck_34xx; } + if (omap3_has_192mhz_clk()) + omap_96m_alwon_fck = omap_96m_alwon_fck_3630; clk_init(&omap2_clk_functions); diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index c81ec27..1bd52dc 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -336,6 +336,8 @@ #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) #define OMAP3430_CLKSEL_L3_SHIFT 0 #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) +#define OMAP3630_CLKSEL_96M_SHIFT 12 +#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) /* CM_CLKSTCTRL_CORE */ #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index a091b53..764334a 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -175,6 +175,8 @@ void __init omap3_check_features(void) OMAP3_CHECK_FEATURE(status, SGX); OMAP3_CHECK_FEATURE(status, NEON); OMAP3_CHECK_FEATURE(status, ISP); + if (cpu_is_omap3630()) + omap3_features |= OMAP3_HAS_192MHZ_CLK; /* * TODO: Get additional info (where applicable) @@ -341,6 +343,7 @@ void __init omap3_cpuinfo(void) OMAP3_SHOW_FEATURE(sgx); OMAP3_SHOW_FEATURE(neon); OMAP3_SHOW_FEATURE(isp); + OMAP3_SHOW_FEATURE(192mhz_clk); printk(")\n"); } diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 9a028bd..6718e40 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -500,6 +500,7 @@ extern u32 omap3_features; #define OMAP3_HAS_SGX BIT(2) #define OMAP3_HAS_NEON BIT(3) #define OMAP3_HAS_ISP BIT(4) +#define OMAP3_HAS_192MHZ_CLK BIT(5) #define OMAP3_HAS_FEATURE(feat,flag) \ static inline unsigned int omap3_has_ ##feat(void) \ @@ -512,5 +513,6 @@ OMAP3_HAS_FEATURE(sgx, SGX) OMAP3_HAS_FEATURE(iva, IVA) OMAP3_HAS_FEATURE(neon, NEON) OMAP3_HAS_FEATURE(isp, ISP) +OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) #endif