From patchwork Thu Feb 18 22:33:48 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: omar ramirez X-Patchwork-Id: 80467 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o1IMLDn2007703 for ; Thu, 18 Feb 2010 22:21:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758730Ab0BRWVO (ORCPT ); Thu, 18 Feb 2010 17:21:14 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:58155 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755304Ab0BRWVN (ORCPT ); Thu, 18 Feb 2010 17:21:13 -0500 Received: from dlep36.itg.ti.com ([157.170.170.91]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o1IML95f029664 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 18 Feb 2010 16:21:09 -0600 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o1IML87D007611; Thu, 18 Feb 2010 16:21:08 -0600 (CST) Received: from Matrix (matrix.am.dhcp.ti.com [128.247.75.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o1IML8Z24150; Thu, 18 Feb 2010 16:21:08 -0600 (CST) Received: by Matrix (Postfix, from userid 1003) id 453404105FF; Thu, 18 Feb 2010 16:33:50 -0600 (CST) From: Omar Ramirez Luna To: linux-omap Cc: Ameya Palande , Hiroshi Doyu , Felipe Contreras , Nishanth Menon , Omar Ramirez Luna , Hiroshi DOYU Subject: [RFC][PATCH 1/2] DSPBRIDGE: add checking 128 byte alignment for dsp cache line size Date: Thu, 18 Feb 2010 16:33:48 -0600 Message-Id: <1266532429-30927-2-git-send-email-omar.ramirez@ti.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1266532429-30927-1-git-send-email-omar.ramirez@ti.com> References: <1266532429-30927-1-git-send-email-omar.ramirez@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 18 Feb 2010 22:21:16 +0000 (UTC) diff --git a/drivers/dsp/bridge/Kconfig b/drivers/dsp/bridge/Kconfig index e494f02..646fdcb 100644 --- a/drivers/dsp/bridge/Kconfig +++ b/drivers/dsp/bridge/Kconfig @@ -35,6 +35,23 @@ config BRIDGE_DEBUG help Say Y to enable Bridge debugging capabilities +menu "Bridge Hacking" + depends on MPU_BRIDGE + +config BRIDGE_CACHE_LINE_CHECK + bool "Check buffers to be 128 byte aligned" + depends on MPU_BRIDGE + default n + help + When the DSP processes data, the DSP cache controller loads 128-Byte + chunks (lines) from SDRAM and writes the data back in 128-Byte chunks. + If a DMM buffer does not start and end on a 128-Byte boundary, the data + preceding the start address (SA) from the 128-Byte boundary to the SA + and the data at addresses trailing the end address (EA) from the EA to + the next 128-Byte boundary will be loaded and written back as well. + This can lead to heap corruption. Say Y, to enforce the check for 128 + byte alignment, buffers failing this check will be rejected. + comment "Bridge Notifications" depends on MPU_BRIDGE @@ -45,3 +62,5 @@ config BRIDGE_NTFY_PWRERR Enable notifications to registered clients on the event of power errror trying to suspend bridge driver. Say Y, to signal this event as a fatal error, this will require a bridge restart to recover. + +endmenu diff --git a/drivers/dsp/bridge/rmgr/proc.c b/drivers/dsp/bridge/rmgr/proc.c index 6c0173a..78a31ef 100644 --- a/drivers/dsp/bridge/rmgr/proc.c +++ b/drivers/dsp/bridge/rmgr/proc.c @@ -69,6 +69,8 @@ #define PWR_TIMEOUT 500 /* Sleep/wake timout in msec */ #define EXTEND "_EXT_END" /* Extmem end addr in DSP binary */ +#define DSP_CACHE_LINE 128 + extern char *iva_img; /* ----------------------------------- Globals */ @@ -1293,6 +1295,16 @@ DSP_STATUS PROC_Map(DSP_HPROCESSOR hProcessor, void *pMpuAddr, u32 ulSize, "hProcessor %x, pMpuAddr %x, ulSize %x, pReqAddr %x, " "ulMapAttr %x, ppMapAddr %x\n", hProcessor, pMpuAddr, ulSize, pReqAddr, ulMapAttr, ppMapAddr); + +#ifdef CONFIG_BRIDGE_CACHE_LINE_CHECK + if (!IS_ALIGNED((u32)pMpuAddr, DSP_CACHE_LINE) || + !IS_ALIGNED(size, DSP_CACHE_LINE)) { + pr_err("%s: not aligned: 0x%x (%d)\n", __func__, + (u32)pMpuAddr, ulSize); + return -EFAULT; + } +#endif + /* Calculate the page-aligned PA, VA and size */ vaAlign = PG_ALIGN_LOW((u32) pReqAddr, PG_SIZE_4K); paAlign = PG_ALIGN_LOW((u32) pMpuAddr, PG_SIZE_4K);