@@ -71,6 +71,12 @@
#define DSP_CACHE_LINE 128
+#define BUFMODE_MASK (3 << 14)
+
+/* Buffer modes from DSP perspective */
+#define RBUF 0x1 /* Input buffer */
+#define WBUF 0x2 /* Output Buffer */
+
extern char *iva_img;
/* ----------------------------------- Globals */
@@ -1297,11 +1303,13 @@ DSP_STATUS PROC_Map(DSP_HPROCESSOR hProcessor, void *pMpuAddr, u32 ulSize,
pReqAddr, ulMapAttr, ppMapAddr);
#ifdef CONFIG_BRIDGE_CACHE_LINE_CHECK
- if (!IS_ALIGNED((u32)pMpuAddr, DSP_CACHE_LINE) ||
- !IS_ALIGNED(size, DSP_CACHE_LINE)) {
- pr_err("%s: not aligned: 0x%x (%d)\n", __func__,
+ if ((ulMapAttr & BUFMODE_MASK) != RBUF) {
+ if (!IS_ALIGNED((u32)pMpuAddr, DSP_CACHE_LINE) ||
+ !IS_ALIGNED(ulSize, DSP_CACHE_LINE)) {
+ pr_err("%s: not aligned: 0x%x (%d)\n", __func__,
(u32)pMpuAddr, ulSize);
- return -EFAULT;
+ return -EFAULT;
+ }
}
#endif