@@ -431,22 +431,22 @@ dsp_status sm_interrupt_dsp(struct wmd_dev_context *dev_context, u16 mb_val)
* 2:0 AUTO_IVA2_DPLL - Enabling IVA2 DPLL auto control
* in CM_AUTOIDLE_PLL_IVA2 register
*/
- *(reg_uword32 *) (resources.dw_cm_base + 0x34) = 0x1;
+ *(reg_uword32 *) ((u32)(resources.dw_cm_base) + 0x34) = 0x1;
/*
* 7:4 IVA2_DPLL_FREQSEL - IVA2 internal frq set to
* 0.75 MHz - 1.0 MHz
* 2:0 EN_IVA2_DPLL - Enable IVA2 DPLL in lock mode
*/
- temp = *(reg_uword32 *) (resources.dw_cm_base + 0x4);
+ temp = *(reg_uword32 *) ((u32)(resources.dw_cm_base) + 0x4);
temp = (temp & 0xFFFFFF08) | 0x37;
- *(reg_uword32 *) (resources.dw_cm_base + 0x4) = temp;
+ *(reg_uword32 *) ((u32)(resources.dw_cm_base) + 0x4) = temp;
/* Restore mailbox settings */
omap_mbox_restore_ctx(dev_context->mbox);
/* Access MMU SYS CONFIG register to generate a short wakeup */
- temp = *(reg_uword32 *) (resources.dw_dmmu_base + 0x10);
+ temp = *(reg_uword32 *) ((u32)(resources.dw_dmmu_base) + 0x10);
dev_context->dw_brd_state = BRD_RUNNING;
} else if (dev_context->dw_brd_state == BRD_RETENTION) {
@@ -462,4 +462,4 @@ dsp_status sm_interrupt_dsp(struct wmd_dev_context *dev_context, u16 mb_val)
}
return DSP_SOK;
-}
\ No newline at end of file
+}