From patchwork Wed Mar 31 15:35:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Balbi X-Patchwork-Id: 89968 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2VFZrAi001763 for ; Wed, 31 Mar 2010 15:36:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757006Ab0CaPgE (ORCPT ); Wed, 31 Mar 2010 11:36:04 -0400 Received: from smtp.nokia.com ([192.100.105.134]:61012 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756997Ab0CaPgD (ORCPT ); Wed, 31 Mar 2010 11:36:03 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2VFZhNs026236; Wed, 31 Mar 2010 10:35:58 -0500 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 31 Mar 2010 18:35:47 +0300 Received: from mgw-da02.ext.nokia.com ([147.243.128.26]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 31 Mar 2010 18:35:46 +0300 Received: from localhost.localdomain (esdhcp04088.research.nokia.com [172.21.40.88]) by mgw-da02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o2VFZaV8021418; Wed, 31 Mar 2010 18:35:41 +0300 From: Felipe Balbi To: David Brownell Cc: Tony Lindgren , Mark Brown , Linux OMAP Mailing List , Felipe Balbi Subject: [RFC/PATCHv2 2/4] arm: omap: gpio: implement set_debounce method Date: Wed, 31 Mar 2010 18:35:10 +0300 Message-Id: <1270049712-28272-3-git-send-email-felipe.balbi@nokia.com> X-Mailer: git-send-email 1.7.0.rc0.33.g7c3932 In-Reply-To: <1270038435-28106-1-git-send-email-felipe.balbi@nokia.com> References: <1270038435-28106-1-git-send-email-felipe.balbi@nokia.com> X-OriginalArrivalTime: 31 Mar 2010 15:35:46.0758 (UTC) FILETIME=[D5451E60:01CAD0E7] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 31 Mar 2010 15:36:11 +0000 (UTC) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 76a347b..345ed2c 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -612,6 +612,59 @@ do { \ __raw_writel(l, base + reg); \ } while(0) +/** + * _set_gpio_debounce - low level gpio debounce time + * @bank: the gpio bank we're acting upon + * @gpio: the gpio number on this @gpio + * @debounce: debounce time to use + * + * OMAP's debounce time is in 31us steps so we need + * to convert and round up to the closest unit. + */ +static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, + unsigned debounce) +{ + void __iomem *reg = bank->base; + u32 val; + u32 l; + + if (debounce < 32) + debounce = 0x01; + else if (debounce > 7936) + debounce = 0xff; + else + debounce = (debounce / 0x1f) - 1; + + l = 1 << get_gpio_index(gpio); + + if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_DEBOUNCINGTIME; + else + reg += OMAP24XX_GPIO_DEBOUNCE_VAL; + + __raw_writel(debounce, reg); + + reg = bank->base; + if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_DEBOUNCENABLE; + else + reg += OMAP24XX_GPIO_DEBOUNCE_EN; + + val = __raw_readl(reg); + + if (debounce) { + val |= l; + if (cpu_is_omap34xx() || cpu_is_omap44xx()) + clk_enable(bank->dbck); + } else { + val &= ~l; + if (cpu_is_omap34xx() || cpu_is_omap44xx()) + clk_disable(bank->dbck); + } + + __raw_writel(val, reg); +} + void omap_set_gpio_debounce(int gpio, int enable) { struct gpio_bank *bank; @@ -1608,6 +1661,20 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) return 0; } +static int gpio_debounce(struct gpio_chip *chip, unsigned offset, + unsigned debounce) +{ + struct gpio_bank *bank; + unsigned long flags; + + bank = container_of(chip, struct gpio_bank, chip); + spin_lock_irqsave(&bank->lock, flags); + _set_gpio_debounce(bank, offset, value); + spin_unlock_irqrestore(&bank->lock, flags); + + return 0; +} + static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) { struct gpio_bank *bank; @@ -1860,6 +1927,7 @@ static int __init _omap_gpio_init(void) bank->chip.direction_input = gpio_input; bank->chip.get = gpio_get; bank->chip.direction_output = gpio_output; + bank->chip.set_debounce = gpio_debounce; bank->chip.set = gpio_set; bank->chip.to_irq = gpio_2irq; if (bank_is_mpuio(bank)) {