From patchwork Thu Apr 1 17:16:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gurav , Pramod" X-Patchwork-Id: 90116 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o31BdcbU009997 for ; Thu, 1 Apr 2010 11:40:00 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755484Ab0DALjk (ORCPT ); Thu, 1 Apr 2010 07:39:40 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:55331 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755443Ab0DALjg (ORCPT ); Thu, 1 Apr 2010 07:39:36 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o31BdXXf005374 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 1 Apr 2010 06:39:35 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o31BdUtD025714; Thu, 1 Apr 2010 17:09:32 +0530 (IST) From: Pramod Gurav To: linux-omap@vger.kernel.org Cc: Pramod Gurav , Vishwanath Sripathy , Ambresh K Subject: [PATCH v1 2/2] OMAP3630 SDRC: Change in DVFS Latency Formula for OMAP3630 Date: Fri, 2 Apr 2010 01:16:56 +0800 Message-Id: <1270142216-18118-3-git-send-email-pramod.gurav@ti.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1270142216-18118-2-git-send-email-pramod.gurav@ti.com> References: <> <1270142216-18118-1-git-send-email-pramod.gurav@ti.com> <1270142216-18118-2-git-send-email-pramod.gurav@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Apr 2010 11:40:03 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index 6ad18f2..af0807a 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -39,6 +39,12 @@ #define SHIFT_DPLL_M 16 #define SHIFT_DPLL_N 8 #define SHIFT_DPLL_M2 27 + +/* + * While calculating M2 stabilization delay, especially the formula + * used for 3630 computes to zero. So to avoid calculation truncating to + * zero, SCALING_FACTOR is used appropriately. + */ #define SCALING_FACTOR 10 /* @@ -107,12 +113,21 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sys_clk = (1 << SCALING_FACTOR) / sys_clk_rate; clkoutx2 = (sys_clk * (n + 1) * m2) / (2 * m); - /* wait time for L3 clk stabilization = 4*REFCLK + 8*CLKOUTX2 */ - refclk = (n + 1) * sys_clk; - switch_latency = (4 * refclk) + (8 * clkoutx2); - - /* Adding 2000 ns to sdrc clk stab */ - sdrc_clk_stab = switch_latency + 2000; + /* + * wait time for L3 clk stabilization + * for OMAP3430 = 4*REFCLK + 8*CLKOUTX2 + * for OMAP3630 = 2*REFCLK + 8*CLKOUTX2 + */ + if (cpu_is_omap3630()) { + switch_latency = (2 * sys_clk) + (10 * clkoutx2); + /* Adding 1000 nano seconds to sdrc clk stab */ + sdrc_clk_stab = switch_latency + 1000; + } else { + refclk = (n + 1) * sys_clk; + switch_latency = (4 * refclk) + (8 * clkoutx2); + /* Adding 2000 ns to sdrc clk stab */ + sdrc_clk_stab = switch_latency + 2000; + } /* * Calculate the number of MPU cycles