From patchwork Tue Apr 6 16:51:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laine Walker-Avina X-Patchwork-Id: 90808 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o36H1tbV022467 for ; Tue, 6 Apr 2010 17:02:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757466Ab0DFRB5 (ORCPT ); Tue, 6 Apr 2010 13:01:57 -0400 Received: from exprod7og117.obsmtp.com ([64.18.2.6]:35294 "HELO exprod7og117.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1757089Ab0DFRB4 (ORCPT ); Tue, 6 Apr 2010 13:01:56 -0400 Received: from source ([204.130.249.21]) by exprod7ob117.postini.com ([64.18.6.12]) with SMTP ID DSNKS7tpAlGNgb1Z9VJg9ePBbpfvSGy2n+3U@postini.com; Tue, 06 Apr 2010 10:01:55 PDT Received: from localhost.localdomain ([172.16.2.46]) by p21.roseville.pasco.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 6 Apr 2010 09:52:21 -0700 From: Laine Walker-Avina To: linux-omap@vger.kernel.org Cc: Laine Walker-Avina Subject: [PATCH 3/5] OMAP: Add SDRAM timings for Micron mt46h16m32lf-6 Date: Tue, 6 Apr 2010 09:51:06 -0700 Message-Id: <1270572668-2336-4-git-send-email-lwalkera@ieee.org> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1270572668-2336-3-git-send-email-lwalkera@ieee.org> References: <1270572668-2336-1-git-send-email-lwalkera@ieee.org> <1270572668-2336-2-git-send-email-lwalkera@ieee.org> <1270572668-2336-3-git-send-email-lwalkera@ieee.org> X-OriginalArrivalTime: 06 Apr 2010 16:52:21.0312 (UTC) FILETIME=[8650EC00:01CAD5A9] Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 06 Apr 2010 17:02:06 +0000 (UTC) diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h16m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h16m32lf-6.h new file mode 100644 index 0000000..5e7c3e8 --- /dev/null +++ b/arch/arm/mach-omap2/sdram-micron-mt46h16m32lf-6.h @@ -0,0 +1,67 @@ +/* + * SDRC register values for the Micron MT46H16M32LF-6 + * + * Copyright (C) 2010 PASCO scientifc + * + * Laine Walker-Avina + * + * Based on the file for the Micron MT46H32M32LF-6 by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H16M32LF +#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H16M32LF + +#include + +/* Micron MT46H16M32LF-6 */ +static struct omap_sdrc_params mt46h16m32lf6_sdrc_params[] = { + [0] = { + .rate = 166000000, + .actim_ctrla = ACTIM_TRFC(17) | ACTIM_TRC(10) | ACTIM_TRAS(7) | + ACTIM_TRP(3) | ACTIM_TRCD(3) | ACTIM_TRRD(2) | ACTIM_TDPL(3) | + ACTIM_TDAL(6), + .actim_ctrlb = ACTIM_TWTR(2) | ACTIM_TCKE(1) | ACTIM_TXP(1) | + ACTIM_TXSR(20), + .rfr_ctrl = RFR_CTRL_ARCV(1244) | RFR_CTRL_ARE(1), + .mr = MR_WBST(0) | MR_CASL(3) | MR_BL(2), + }, + [1] = { + .rate = 165941176, + .actim_ctrla = ACTIM_TRFC(17) | ACTIM_TRC(10) | ACTIM_TRAS(7) | + ACTIM_TRP(3) | ACTIM_TRCD(3) | ACTIM_TRRD(2) | ACTIM_TDPL(3) | + ACTIM_TDAL(6), + .actim_ctrlb = ACTIM_TWTR(2) | ACTIM_TCKE(1) | ACTIM_TXP(1) | + ACTIM_TXSR(20), + .rfr_ctrl = RFR_CTRL_ARCV(1244) | RFR_CTRL_ARE(1), + .mr = MR_WBST(0) | MR_CASL(3) | MR_BL(2), + }, + [2] = { + .rate = 83000000, + .actim_ctrla = ACTIM_TRFC(9) | ACTIM_TRC(5) | ACTIM_TRAS(4) | + ACTIM_TRP(2) | ACTIM_TRCD(2) | ACTIM_TRRD(1) | ACTIM_TDPL(2) | + ACTIM_TDAL(3), + .actim_ctrlb = ACTIM_TWTR(1) | ACTIM_TCKE(1) | ACTIM_TXP(1) | + ACTIM_TXSR(10), + .rfr_ctrl = RFR_CTRL_ARCV(597) | RFR_CTRL_ARE(1), + .mr = MR_WBST(0) | MR_CASL(3) | MR_BL(2), + }, + [3] = { + .rate = 82970588, + .actim_ctrla = ACTIM_TRFC(10) | ACTIM_TRC(5) | ACTIM_TRAS(4) | + ACTIM_TRP(2) | ACTIM_TRCD(2) | ACTIM_TRRD(1) | ACTIM_TDPL(2) | + ACTIM_TDAL(3), + .actim_ctrlb = ACTIM_TWTR(1) | ACTIM_TCKE(1) | ACTIM_TXP(2) | + ACTIM_TXSR(12), + .rfr_ctrl = RFR_CTRL_ARCV(597) | RFR_CTRL_ARE(1), + .mr = MR_WBST(0) | MR_CASL(3) | MR_BL(2), + }, + [4] = { + .rate = 0 + }, +}; + +#endif