From patchwork Thu Apr 8 17:54:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 91336 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o38HsbK2005127 for ; Thu, 8 Apr 2010 17:54:56 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932986Ab0DHRy0 (ORCPT ); Thu, 8 Apr 2010 13:54:26 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:45733 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932955Ab0DHRyX (ORCPT ); Thu, 8 Apr 2010 13:54:23 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o38HsIhU030911 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Apr 2010 12:54:18 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o38HsC6u003088; Thu, 8 Apr 2010 12:54:12 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.75.1]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o38HsCZ16527; Thu, 8 Apr 2010 12:54:12 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id 20390C240; Thu, 8 Apr 2010 12:54:11 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Deepak K , Govindraj R , Kevin Hilman , Tero Kristo , Nishanth Menon Subject: [PM][PATCH 2/4] OMAP3: Serial: Errata i202: fix for MDR1 access Date: Thu, 8 Apr 2010 12:54:07 -0500 Message-Id: <1270749249-14041-3-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1270749249-14041-2-git-send-email-nm@ti.com> References: <1270749249-14041-1-git-send-email-nm@ti.com> <1270749249-14041-2-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Apr 2010 17:54:57 +0000 (UTC) diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 86d3b47..144033f 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -223,6 +223,19 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) uart->context_valid = 0; serial_write_reg(p, UART_OMAP_MDR1, 0x7); + /* + * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) + * The access to uart register after MDR1 Access + * causes UART to corrupt data. + * + * Need a delay = + * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) + * give 10 times as much + */ + udelay(2); + /* TX and RX FIFO Clear; FIFO dis */ + serial_write_reg(p, UART_FCR, 0xA6); + serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ efr = serial_read_reg(p, UART_EFR); serial_write_reg(p, UART_EFR, UART_EFR_ECB); @@ -235,7 +248,6 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) serial_write_reg(p, UART_IER, uart->ier); serial_write_reg(p, UART_LCR, 0x80); serial_write_reg(p, UART_MCR, uart->mcr); - serial_write_reg(p, UART_FCR, 0xA1); serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ serial_write_reg(p, UART_EFR, efr); serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); @@ -243,6 +255,10 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) serial_write_reg(p, UART_OMAP_WER, uart->wer); serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ + /* Errata: i202 */ + udelay(2); + /* TX and RX FIFO Clear; FIFO en */ + serial_write_reg(p, UART_FCR, 0xA7); } #else static inline void omap_uart_save_context(struct omap_uart_state *uart) {}