From patchwork Fri Apr 9 20:31:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 91787 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o39KWKrM005922 for ; Fri, 9 Apr 2010 20:32:21 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756971Ab0DIUcT (ORCPT ); Fri, 9 Apr 2010 16:32:19 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39554 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756257Ab0DIUcS (ORCPT ); Fri, 9 Apr 2010 16:32:18 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o39KW6Id031810 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 9 Apr 2010 15:32:06 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o39KW1S0010963; Fri, 9 Apr 2010 15:32:01 -0500 (CDT) Received: from senorita (senorita.am.dhcp.ti.com [128.247.75.1]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o39KW1Z11191; Fri, 9 Apr 2010 15:32:01 -0500 (CDT) Received: by senorita (Postfix, from userid 1000) id C9C5CC1F6; Fri, 9 Apr 2010 15:32:00 -0500 (CDT) From: Nishanth Menon To: linux-omap Cc: Deepak K , Govindraj R , Kevin Hilman , Tero Kristo , Nishanth Menon Subject: [PM][PATCH v2 2/4] OMAP3: Serial: Errata i202: fix for MDR1 access Date: Fri, 9 Apr 2010 15:31:47 -0500 Message-Id: <1270845107-6236-1-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <[PM][PATCH 2/4] OMAP3: Serial: Errata i202: fix for MDR1 access> References: <[PM][PATCH 2/4] OMAP3: Serial: Errata i202: fix for MDR1 access> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 09 Apr 2010 20:32:22 +0000 (UTC) diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index a7c45b5..78091e4 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -185,6 +185,41 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart) #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) +/* + * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) + * The access to uart register after MDR1 Access + * causes UART to corrupt data. + * + * Need a delay = + * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) + * give 10 times as much + */ +static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, + u8 fcr_val) +{ + struct plat_serial8250_port *p = uart->p; + u8 timeout = 255; + + serial_write_reg(p, UART_OMAP_MDR1, mdr1_val); + udelay(2); + /* Add TX and RX FIFO Clear */ + serial_write_reg(p, UART_FCR, fcr_val | 0x06); + /* + * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and + * TX_FIFO_E bit is 1. So, we check for 0x20 being read. + */ + while (0x20 != (serial_read_reg(p, UART_LSR) & 0x21)) { + timeout--; + if (!timeout) { + /* Should *never* happen. we warn and carry on */ + dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n", + serial_read_reg(p, UART_LSR)); + break; + } + udelay(1); + } +} + static void omap_uart_save_context(struct omap_uart_state *uart) { u16 lcr = 0; @@ -222,7 +257,7 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) uart->context_valid = 0; - serial_write_reg(p, UART_OMAP_MDR1, 0x7); + omap_uart_mdr1_errataset(uart, 0x07, 0xA0); serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ efr = serial_read_reg(p, UART_EFR); serial_write_reg(p, UART_EFR, UART_EFR_ECB); @@ -235,14 +270,13 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) serial_write_reg(p, UART_IER, uart->ier); serial_write_reg(p, UART_LCR, 0x80); serial_write_reg(p, UART_MCR, uart->mcr); - serial_write_reg(p, UART_FCR, 0xA1); serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ serial_write_reg(p, UART_EFR, efr); serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); serial_write_reg(p, UART_OMAP_SCR, uart->scr); serial_write_reg(p, UART_OMAP_WER, uart->wer); serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); - serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ + omap_uart_mdr1_errataset(uart, 0x00, 0xA1); } #else static inline void omap_uart_save_context(struct omap_uart_state *uart) {}