@@ -24,19 +24,13 @@
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Alexander Shishkin");
-/* Cortex CoreSight components within omap3xxx EMU */
-#define ETM_BASE (L4_EMU_34XX_PHYS + 0x10000)
-#define DBG_BASE (L4_EMU_34XX_PHYS + 0x11000)
-#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000)
-#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000)
-
static struct amba_device omap3_etb_device = {
.dev = {
.init_name = "etb",
},
.res = {
- .start = ETB_BASE,
- .end = ETB_BASE + SZ_4K - 1,
+ .start = OMAP34XX_ETB_PHYS,
+ .end = OMAP34XX_ETB_PHYS + OMAP34XX_ETB_SIZE - 1,
.flags = IORESOURCE_MEM,
},
.periphid = 0x000bb907,
@@ -47,8 +41,8 @@ static struct amba_device omap3_etm_device = {
.init_name = "etm",
},
.res = {
- .start = ETM_BASE,
- .end = ETM_BASE + SZ_4K - 1,
+ .start = OMAP34XX_ETM_PHYS,
+ .end = OMAP34XX_ETM_PHYS + OMAP34XX_ETM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
.periphid = 0x102bb921,
@@ -185,6 +185,26 @@
/* 3430 IVA - currently unmapped */
+#define OMAP34XX_DBG_OFFSET (0x00011000)
+#define OMAP34XX_DBG_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_DBG_OFFSET)
+#define OMAP34XX_DBG_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_DBG_OFFSET)
+#define OMAP34XX_DBG_SIZE SZ_4K
+
+#define OMAP34XX_ETM_OFFSET (0x00010000)
+#define OMAP34XX_ETM_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_ETM_OFFSET)
+#define OMAP34XX_ETM_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_ETM_OFFSET)
+#define OMAP34XX_ETM_SIZE SZ_4K
+
+#define OMAP34XX_ETB_OFFSET (0x0001b000)
+#define OMAP34XX_ETB_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_ETB_OFFSET)
+#define OMAP34XX_ETB_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_ETB_OFFSET)
+#define OMAP34XX_ETB_SIZE SZ_4K
+
+#define OMAP34XX_DAP_OFFSET (0x0001d000)
+#define OMAP34XX_DAP_VIRT (L4_EMU_34XX_VIRT + OMAP34XX_DAP_OFFSET)
+#define OMAP34XX_DAP_PHYS (L4_EMU_34XX_PHYS + OMAP34XX_DAP_OFFSET)
+#define OMAP34XX_DAP_SIZE SZ_4K
+
/*
* ----------------------------------------------------------------------------
* Omap4 specific IO mapping