From patchwork Mon May 17 10:02:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Balbi X-Patchwork-Id: 100074 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4HA6hrA007824 for ; Mon, 17 May 2010 10:06:43 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754309Ab0EQKFP (ORCPT ); Mon, 17 May 2010 06:05:15 -0400 Received: from smtp.nokia.com ([192.100.122.233]:50177 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752502Ab0EQKFL (ORCPT ); Mon, 17 May 2010 06:05:11 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4HA4BNP016726; Mon, 17 May 2010 13:04:36 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 17 May 2010 13:04:33 +0300 Received: from mgw-da02.ext.nokia.com ([147.243.128.26]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 17 May 2010 13:04:32 +0300 Received: from scadufax.research.nokia.com (esdhcp041223.research.nokia.com [172.21.41.223]) by mgw-da02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o4HA4Ma5012842; Mon, 17 May 2010 13:04:28 +0300 From: felipe.balbi@nokia.com To: Linux OMAP Mailing List Cc: Linux Kernel Mailing List , Tony Lindgren , David Brownell , Andrew Morton , Mark Brown , Felipe Balbi Subject: [PATCH 2/5] arm: omap: gpio: implement set_debounce method Date: Mon, 17 May 2010 13:02:31 +0300 Message-Id: <1274090554-19420-3-git-send-email-felipe.balbi@nokia.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1274090554-19420-1-git-send-email-felipe.balbi@nokia.com> References: <1274090554-19420-1-git-send-email-felipe.balbi@nokia.com> X-OriginalArrivalTime: 17 May 2010 10:04:33.0052 (UTC) FILETIME=[59087DC0:01CAF5A8] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 17 May 2010 10:06:43 +0000 (UTC) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 45a225d..4a17dc4 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -612,6 +612,59 @@ do { \ __raw_writel(l, base + reg); \ } while(0) +/** + * _set_gpio_debounce - low level gpio debounce time + * @bank: the gpio bank we're acting upon + * @gpio: the gpio number on this @gpio + * @debounce: debounce time to use + * + * OMAP's debounce time is in 31us steps so we need + * to convert and round up to the closest unit. + */ +static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, + unsigned debounce) +{ + void __iomem *reg = bank->base; + u32 val; + u32 l; + + if (debounce < 32) + debounce = 0x01; + else if (debounce > 7936) + debounce = 0xff; + else + debounce = (debounce / 0x1f) - 1; + + l = 1 << get_gpio_index(gpio); + + if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_DEBOUNCINGTIME; + else + reg += OMAP24XX_GPIO_DEBOUNCE_VAL; + + __raw_writel(debounce, reg); + + reg = bank->base; + if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_DEBOUNCENABLE; + else + reg += OMAP24XX_GPIO_DEBOUNCE_EN; + + val = __raw_readl(reg); + + if (debounce) { + val |= l; + if (cpu_is_omap34xx() || cpu_is_omap44xx()) + clk_enable(bank->dbck); + } else { + val &= ~l; + if (cpu_is_omap34xx() || cpu_is_omap44xx()) + clk_disable(bank->dbck); + } + + __raw_writel(val, reg); +} + void omap_set_gpio_debounce(int gpio, int enable) { struct gpio_bank *bank; @@ -1608,6 +1661,20 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) return 0; } +static int gpio_debounce(struct gpio_chip *chip, unsigned offset, + unsigned debounce) +{ + struct gpio_bank *bank; + unsigned long flags; + + bank = container_of(chip, struct gpio_bank, chip); + spin_lock_irqsave(&bank->lock, flags); + _set_gpio_debounce(bank, offset, debounce); + spin_unlock_irqrestore(&bank->lock, flags); + + return 0; +} + static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) { struct gpio_bank *bank; @@ -1860,6 +1927,7 @@ static int __init _omap_gpio_init(void) bank->chip.direction_input = gpio_input; bank->chip.get = gpio_get; bank->chip.direction_output = gpio_output; + bank->chip.set_debounce = gpio_debounce; bank->chip.set = gpio_set; bank->chip.to_irq = gpio_2irq; if (bank_is_mpuio(bank)) {