From patchwork Mon May 17 23:12:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kanigeri, Hari" X-Patchwork-Id: 100259 X-Patchwork-Delegate: hiroshi.doyu@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4HN6eMU001171 for ; Mon, 17 May 2010 23:06:40 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756247Ab0EQXGb (ORCPT ); Mon, 17 May 2010 19:06:31 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:60555 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754070Ab0EQXGa (ORCPT ); Mon, 17 May 2010 19:06:30 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4HN6PQK024729 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 17 May 2010 18:06:25 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o4HN6OWe011826; Mon, 17 May 2010 18:06:24 -0500 (CDT) Received: from localhost (matrix.am.dhcp.ti.com [128.247.75.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o4HN6OP17530; Mon, 17 May 2010 18:06:24 -0500 (CDT) From: Hari Kanigeri To: linux omap , Hiroshi Doyu Cc: Tony Lindgren , Hari Kanigeri Subject: [PATCH 1/2] omap: iommu-update irq mask to be specific about twl Date: Mon, 17 May 2010 18:12:29 -0500 Message-Id: <1274137950-18759-2-git-send-email-h-kanigeri2@ti.com> X-Mailer: git-send-email 1.7.0 In-Reply-To: <1274137950-18759-1-git-send-email-h-kanigeri2@ti.com> References: <1274137950-18759-1-git-send-email-h-kanigeri2@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 17 May 2010 23:06:41 +0000 (UTC) diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index e82da68..fcf4f4a 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -46,7 +46,13 @@ #define MMU_IRQ_TLBMISS (1 << 0) #define MMU_IRQ_MASK \ (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ - MMU_IRQ_TRANSLATIONFAULT) + MMU_IRQ_TRANSLATIONFAULT | MMU_IRQ_TLBMISS) +#define MMU_IRQ_TWL_MASK \ + (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ + MMU_IRQ_TRANSLATIONFAULT) +#define MMU_IRQ_TLB_MISS_MASK \ + (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TLBMISS | MMU_IRQ_EMUMISS | \ + MMU_IRQ_TRANSLATIONFAULT) /* MMU_CNTL */ #define MMU_CNTL_SHIFT 1 @@ -96,7 +102,7 @@ static int omap2_iommu_enable(struct iommu *obj) l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); iommu_write_reg(obj, l, MMU_SYSCONFIG); - iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE); + iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); iommu_write_reg(obj, pa, MMU_TTB); l = iommu_read_reg(obj, MMU_CNTL);