From patchwork Thu May 20 21:10:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kanigeri, Hari" X-Patchwork-Id: 101240 X-Patchwork-Delegate: hiroshi.doyu@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4KL45sl001626 for ; Thu, 20 May 2010 21:04:05 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757759Ab0ETVED (ORCPT ); Thu, 20 May 2010 17:04:03 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:43145 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754655Ab0ETVEB (ORCPT ); Thu, 20 May 2010 17:04:01 -0400 Received: from dlep34.itg.ti.com ([157.170.170.115]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4KL3uxx012242 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 20 May 2010 16:03:56 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4KL3rxV003585; Thu, 20 May 2010 16:03:53 -0500 (CDT) Received: from localhost (matrix.am.dhcp.ti.com [128.247.75.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o4KL3rP25673; Thu, 20 May 2010 16:03:53 -0500 (CDT) From: Hari Kanigeri To: Linux Omap , Hiroshi Doyu Cc: Tony Lindgren , Hari Kanigeri , Ramesh Gupta , Hiroshi Doyu Subject: [PATCH 2/2] omap: iommu-add functionality to get TLB miss interrupt Date: Thu, 20 May 2010 16:10:23 -0500 Message-Id: <1274389823-4051-3-git-send-email-h-kanigeri2@ti.com> X-Mailer: git-send-email 1.7.0 In-Reply-To: <1274389823-4051-1-git-send-email-h-kanigeri2@ti.com> References: <1274389823-4051-1-git-send-email-h-kanigeri2@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 20 May 2010 21:04:05 +0000 (UTC) diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index ebbdae2..3cfe1c4 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -65,6 +65,25 @@ ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) + +static void omap2_iommu_set_twl(struct iommu *obj, bool on) +{ + u32 l = iommu_read_reg(obj, MMU_CNTL); + + if (on) + iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); + else + iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); + + l &= ~MMU_CNTL_MASK; + if (on) + l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); + else + l |= (MMU_CNTL_MMU_EN); + + iommu_write_reg(obj, l, MMU_CNTL); +} + static int omap2_iommu_enable(struct iommu *obj) { u32 l, pa; @@ -100,13 +119,9 @@ static int omap2_iommu_enable(struct iommu *obj) l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); iommu_write_reg(obj, l, MMU_SYSCONFIG); - iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); iommu_write_reg(obj, pa, MMU_TTB); - l = iommu_read_reg(obj, MMU_CNTL); - l &= ~MMU_CNTL_MASK; - l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); - iommu_write_reg(obj, l, MMU_CNTL); + omap2_iommu_set_twl(obj, true); return 0; } @@ -304,6 +319,7 @@ static const struct iommu_functions omap2_iommu_ops = { .enable = omap2_iommu_enable, .disable = omap2_iommu_disable, + .set_twl = omap2_iommu_set_twl, .fault_isr = omap2_iommu_fault_isr, .tlb_read_cr = omap2_tlb_read_cr, diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 0752af9..33c7d41 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h @@ -80,6 +80,7 @@ struct iommu_functions { int (*enable)(struct iommu *obj); void (*disable)(struct iommu *obj); + void (*set_twl)(struct iommu *obj, bool on); u32 (*fault_isr)(struct iommu *obj, u32 *ra); void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); @@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); extern u32 iotlb_cr_to_virt(struct cr_regs *cr); extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); +extern void iommu_set_twl(struct iommu *obj, bool on); extern void flush_iotlb_page(struct iommu *obj, u32 da); extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); extern void flush_iotlb_all(struct iommu *obj); diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index b2b3937..aa064e1 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -370,6 +370,23 @@ void flush_iotlb_all(struct iommu *obj) } EXPORT_SYMBOL_GPL(flush_iotlb_all); +/** + * iommu_set_twl - enable/disable table walking logic + * @obj: target iommu + * @on: enable/disable + * + * Function used to enable/disable TWL. If one wants to work + * exclusively with locked TLB entries and receive notifications + * for TLB miss then call this function to disable TWL. + */ +void iommu_set_twl(struct iommu *obj, bool on) +{ + clk_enable(obj->clk); + arch_iommu->set_twl(obj, on); + clk_disable(obj->clk); +} +EXPORT_SYMBOL_GPL(iommu_set_twl); + #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)