@@ -85,5 +85,17 @@
#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
+/* GPIO controller*/
+#define OMAP242X_GPIO1_BASE (L4_24XX_BASE + 0x18000)
+#define OMAP242X_GPIO2_BASE (L4_24XX_BASE + 0x1a000)
+#define OMAP242X_GPIO3_BASE (L4_24XX_BASE + 0x1c000)
+#define OMAP242X_GPIO4_BASE (L4_24XX_BASE + 0x1e000)
+
+#define OMAP243X_GPIO1_BASE (L4_WK_243X_BASE + 0xC000)
+#define OMAP243X_GPIO2_BASE (L4_WK_243X_BASE + 0xE000)
+#define OMAP243X_GPIO3_BASE (L4_WK_243X_BASE + 0x10000)
+#define OMAP243X_GPIO4_BASE (L4_WK_243X_BASE + 0x12000)
+#define OMAP243X_GPIO5_BASE (L4_24XX_BASE + 0xB6000)
+
#endif /* __ASM_ARCH_OMAP2_H */
@@ -87,5 +87,13 @@
#define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000)
#define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000)
+/* GPIO controller*/
+#define OMAP34XX_GPIO1_BASE (L4_WK_34XX_BASE + 0x10000)
+#define OMAP34XX_GPIO2_BASE (L4_PER_34XX_BASE + 0x50000)
+#define OMAP34XX_GPIO3_BASE (L4_PER_34XX_BASE + 0x52000)
+#define OMAP34XX_GPIO4_BASE (L4_PER_34XX_BASE + 0x54000)
+#define OMAP34XX_GPIO5_BASE (L4_PER_34XX_BASE + 0x56000)
+#define OMAP34XX_GPIO6_BASE (L4_PER_34XX_BASE + 0x58000)
+
#endif /* __ASM_ARCH_OMAP3_H */
@@ -52,5 +52,13 @@
#define OMAP4_MMU1_BASE 0x55082000
#define OMAP4_MMU2_BASE 0x4A066000
+/* GPIO controller*/
+#define OMAP44XX_GPIO1_BASE (L4_WK_44XX_BASE + 0x10000)
+#define OMAP44XX_GPIO2_BASE (L4_PER_44XX_BASE + 0x55000)
+#define OMAP44XX_GPIO3_BASE (L4_PER_44XX_BASE + 0x57000)
+#define OMAP44XX_GPIO4_BASE (L4_PER_44XX_BASE + 0x59000)
+#define OMAP44XX_GPIO5_BASE (L4_PER_44XX_BASE + 0x5B000)
+#define OMAP44XX_GPIO6_BASE (L4_PER_44XX_BASE + 0x5D000)
+
#endif /* __ASM_ARCH_OMAP44XX_H */