@@ -44,6 +44,8 @@
#define DISPC_IRQ_WAKEUP (1 << 16)
#define DISPC_IRQ_SYNC_LOST_2 (1 << 17)
#define DISPC_IRQ_VSYNC2 (1 << 18)
+#define DISPC_IRQ_VID3_END_WIN (1 << 19)
+#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
@@ -173,7 +173,8 @@ struct dispc_reg { u16 idx; };
DISPC_IRQ_SYNC_LOST | \
DISPC_IRQ_SYNC_LOST_DIGIT | \
(cpu_is_omap44xx() ? \
- DISPC_IRQ_SYNC_LOST_2 : 0))
+ (DISPC_IRQ_VID3_FIFO_UNDERFLOW | \
+ DISPC_IRQ_SYNC_LOST_2) : 0))
#define DISPC_MAX_NR_ISRS 8
@@ -2540,6 +2541,8 @@ void dispc_dump_irqs(struct seq_file *s)
PIS(VSYNC2);
PIS(ACBIAS_COUNT_STAT2);
PIS(SYNC_LOST_2);
+ PIS(VID3_FIFO_UNDERFLOW);
+ PIS(VID3_END_WIN);
}
#undef PIS
}
@@ -3151,6 +3154,24 @@ static void dispc_error_worker(struct work_struct *work)
}
}
+ if (errors & DISPC_IRQ_VID3_FIFO_UNDERFLOW) {
+ DSSERR("VID3_FIFO_UNDERFLOW, disabling VID2\n");
+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
+ struct omap_overlay *ovl;
+ ovl = omap_dss_get_overlay(i);
+
+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
+ continue;
+
+ if (ovl->id == 3) {
+ dispc_enable_plane(ovl->id, 0);
+ dispc_go(ovl->manager->id);
+ mdelay(50);
+ break;
+ }
+ }
+ }
+
if (errors & DISPC_IRQ_SYNC_LOST) {
struct omap_overlay_manager *manager = NULL;
bool enable = false;