From patchwork Wed Jul 21 16:02:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hunter, Jon" X-Patchwork-Id: 113380 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6LG5mGd024968 for ; Wed, 21 Jul 2010 16:05:49 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755241Ab0GUQFs (ORCPT ); Wed, 21 Jul 2010 12:05:48 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:41252 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754253Ab0GUQFr (ORCPT ); Wed, 21 Jul 2010 12:05:47 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o6LG5kFm002500 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 21 Jul 2010 11:05:46 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o6LG5kMj024401; Wed, 21 Jul 2010 11:05:46 -0500 (CDT) Received: from a0741266-laptop (h0-61.vpn.ti.com [172.24.0.61]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id FBBAfRP20535; Sat, 11 Dec 1915 05:41:27 -0500 (CDT) Received: by a0741266-laptop (Postfix, from userid 1000) id 52B5A204BC; Wed, 21 Jul 2010 11:02:37 -0500 (CDT) From: Jon Hunter To: linux-omap Cc: Jon Hunter Subject: [PATCH] omap3: Prevent SDRC deadlock when L3 is changing frequency Date: Wed, 21 Jul 2010 11:02:35 -0500 Message-Id: <1279728155-2643-1-git-send-email-jon-hunter@ti.com> X-Mailer: git-send-email 1.7.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 21 Jul 2010 16:06:32 +0000 (UTC) diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index de99ba2..e87e730 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll) ldr r4, [sp, #80] str r4, omap_sdrc_mr_1_val skip_cs1_params: + mrc p15, 0, r8, c1, c0, 0 @ read aux ctrl register + bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction + mcr p15, 0, r10, c1, c0, 0 @ write aux ctrl register dsb @ flush buffered writes to interconnect - + isb @ prevent speculative exec past here cmp r3, #1 @ if increasing SDRC clk rate, bleq configure_sdrc @ program the SDRC regs early (for RFR) cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state @@ -148,6 +151,7 @@ skip_cs1_params: beq return_to_sdram @ return to SDRAM code, otherwise, bl configure_sdrc @ reprogram SDRC regs now return_to_sdram: + mcr p15, 0, r8, c1, c0, 0 @ restore aux ctrl register isb @ prevent speculative exec past here mov r0, #0 @ return value ldmfd sp!, {r1-r12, pc} @ restore regs and return