@@ -1,5 +1,5 @@
/*
- * OMAP2/3/4 clockdomain framework functions
+ * OMAP2/3/4 and TI816X clockdomain framework functions
*
* Copyright (C) 2008-2010 Texas Instruments, Inc.
* Copyright (C) 2008-2010 Nokia Corporation
@@ -240,7 +240,7 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
else
bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
- } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ } else if (cpu_is_omap34xx() || cpu_is_omap44xx() || cpu_is_ti816x()) {
if (enable)
bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
else
@@ -812,7 +812,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
- } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ } else if (cpu_is_omap34xx() || cpu_is_omap44xx() || cpu_is_ti816x()) {
u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
__ffs(clkdm->clktrctrl_mask));
@@ -856,7 +856,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
- } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ } else if (cpu_is_omap34xx() || cpu_is_omap44xx() || cpu_is_ti816x()) {
u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
__ffs(clkdm->clktrctrl_mask));
@@ -899,10 +899,10 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
/*
* XXX This should be removed once TI adds wakeup/sleep
- * dependency code and data for OMAP4.
+ * dependency code and data for OMAP4, TI816X
*/
- if (cpu_is_omap44xx()) {
- WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency "
+ if (cpu_is_omap44xx() || cpu_is_ti816x()) {
+ WARN_ONCE(1, "clockdomain: wakeup/sleep dependency "
"support is not yet implemented\n");
} else {
if (atomic_read(&clkdm->usecount) > 0)
@@ -941,10 +941,10 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
/*
* XXX This should be removed once TI adds wakeup/sleep
- * dependency code and data for OMAP4.
+ * dependency code and data for OMAP4, TI816X.
*/
- if (cpu_is_omap44xx()) {
- WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency "
+ if (cpu_is_omap44xx() || cpu_is_ti816x()) {
+ WARN_ONCE(1, "clockdomain: wakeup/sleep dependency "
"support is not yet implemented\n");
} else {
if (atomic_read(&clkdm->usecount) > 0)
@@ -61,6 +61,8 @@ int omap_type(void)
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
+ } else if (cpu_is_ti816x()) {
+ val = omap_ctrl_readl(TI816X_CONTROL_STATUS);
} else {
pr_err("Cannot detect omap type!\n");
goto out;
@@ -319,6 +321,26 @@ static void __init omap4_check_revision(void)
pr_err("Unknown OMAP4 CPU id\n");
}
+void __init ti816x_check_revision(void)
+{
+ u32 idcode;
+ u16 partnum;
+ u8 rev;
+
+ idcode = read_tap_reg(TI816X_CONTROL_DEVICE_ID);
+ partnum = (idcode >> 12) & 0xffff;
+ rev = (idcode >> 28) & 0xff;
+
+ if ((partnum == 0xb81e) && (rev == 0x0)) {
+ omap_revision = TI8168_REV_ES1_0;
+ omap_chip.oc |= CHIP_IS_TI816X;
+ pr_info("OMAP chip is TI8168\n");
+ return;
+ }
+
+ pr_err("Unknown TI816X CPU id\n");
+}
+
#define OMAP3_SHOW_FEATURE(feat) \
if (omap3_has_ ##feat()) \
printk(#feat" ");
@@ -419,6 +441,9 @@ void __init omap2_check_revision(void)
} else if (cpu_is_omap44xx()) {
omap4_check_revision();
return;
+ } else if (cpu_is_ti816x()) {
+ ti816x_check_revision();
+ return;
} else {
pr_err("OMAP revision unknown, please fix!\n");
}
@@ -229,6 +229,17 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
};
#endif
+#ifdef CONFIG_ARCH_TI816X
+static struct map_desc ti816x_io_desc[] __initdata = {
+ {
+ .virtual = L4_SLOW_TI816X_VIRT,
+ .pfn = __phys_to_pfn(L4_SLOW_TI816X_PHYS),
+ .length = L4_SLOW_TI816X_SIZE,
+ .type = MT_DEVICE
+ },
+};
+#endif
+
static void __init _omap2_map_common_io(void)
{
/* Normally devicemaps_init() would flush caches and tlb after
@@ -276,6 +287,14 @@ void __init omap44xx_map_common_io(void)
}
#endif
+#ifdef CONFIG_ARCH_TI816X
+void __init ti816x_map_common_io()
+{
+ iotable_init(ti816x_io_desc, ARRAY_SIZE(ti816x_io_desc));
+ _omap2_map_common_io();
+}
+#endif
+
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
*
@@ -342,7 +361,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
#ifndef CONFIG_PM_RUNTIME
skip_setup_idle = 1;
#endif
- if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */
+ if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4, TI8168 */
omap_hwmod_late_init(skip_setup_idle);
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
@@ -201,6 +201,10 @@ void __init omap_init_irq(void)
base = OMAP24XX_IC_BASE;
else if (cpu_is_omap34xx())
base = OMAP34XX_IC_BASE;
+ else if (cpu_is_ti816x()) {
+ base = TI816X_ARM_INTC_BASE;
+ bank->nr_irqs = 128;
+ }
BUG_ON(!base);
@@ -798,10 +798,11 @@ void __init omap_serial_init_port(int port)
/*
* omap44xx: Never read empty UART fifo
+ * ti816x: Never read when UART fifo empty or write when full
* omap3xxx: Never read empty UART fifo on UARTs
* with IP rev >=0x52
*/
- if (cpu_is_omap44xx())
+ if (cpu_is_omap44xx() || cpu_is_ti816x())
uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)