From patchwork Sat Oct 2 10:36:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 226541 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o92AbKpI011156 for ; Sat, 2 Oct 2010 10:37:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754734Ab0JBKhT (ORCPT ); Sat, 2 Oct 2010 06:37:19 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:58265 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754086Ab0JBKhS (ORCPT ); Sat, 2 Oct 2010 06:37:18 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o92AaVff014801 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 2 Oct 2010 05:36:34 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o92AaLnZ012337; Sat, 2 Oct 2010 16:06:22 +0530 (IST) From: "Varadarajan, Charulatha" To: tony@atomide.com, wim@iguana.be, linux-omap@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, b-cousson@ti.com, rnayak@ti.com, santosh.shilimkar@ti.com, p-basak2@ti.com, "Varadarajan, Charulatha" Subject: [PATCH v2] OMAP2PLUS: WDT: Fix: Disable WDT after reset during init Date: Sat, 2 Oct 2010 16:06:11 +0530 Message-Id: <1286015771-22041-1-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.7.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Sat, 02 Oct 2010 10:37:20 +0000 (UTC) diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 8e2f0aa..6eaec8d 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -916,11 +916,72 @@ static inline void omap_init_vout(void) {} /*-------------------------------------------------------------------------*/ +/* + * Inorder to avoid any assumptions from bootloader regarding WDT + * settings, WDT module is reset during init. This enables the watchdog + * timer. Hence it is required to disable the watchdog after the WDT reset + * during init. Otherwise the system would reboot as per the default + * watchdog timer registers settings. + */ +#define OMAP_WDT_WPS (0x34) +#define OMAP_WDT_SPR (0x48) + +static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused) +{ + void __iomem *base; + int ret; + + if (!oh) { + pr_err("%s: Could not look up wdtimer_hwmod\n", __func__); + return -EINVAL; + } + + base = omap_hwmod_get_mpu_rt_va(oh); + if (!base) { + pr_err("%s: Could not get the base address for %s\n", + oh->name, __func__); + return -EINVAL; + } + + /* Enable the clocks before accessing the WDT registers */ + ret = omap_hwmod_enable(oh); + if (ret) { + pr_err("%s: Could not enable clocks for %s\n", + oh->name, __func__); + return ret; + } + + /* sequence required to disable watchdog */ + __raw_writel(0xAAAA, base + OMAP_WDT_SPR); + while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) + cpu_relax(); + + __raw_writel(0x5555, base + OMAP_WDT_SPR); + while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) + cpu_relax(); + + ret = omap_hwmod_idle(oh); + if (ret) + pr_err("%s: Could not disable clocks for %s\n", + oh->name, __func__); + + return ret; +} + +static void __init omap_disable_wdt(void) +{ + if (cpu_class_is_omap2()) + omap_hwmod_for_each_by_class("wd_timer", + omap2_disable_wdt, NULL); + return; +} + static int __init omap2_init_devices(void) { /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ + omap_disable_wdt(); omap_hsmmc_reset(); omap_init_camera(); omap_init_mbox();