@@ -209,6 +209,55 @@ void omap4_ctrl_pad_writel(u32 val, u16 offset)
__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
}
+/* OMAP DSP control functions */
+
+/**
+ * omap_ctrl_set_dsp_bootaddr - set the DSP's boot address
+ * @pa: DSP boot address (in physical memory)
+ *
+ * Set the DSP's boot address. This is an address in physical memory.
+ * No return value. XXX The TRM claims that this is an "index to a
+ * 4kByte page". If so, why is the bitfield 21 bits wide, rather than
+ * 20?
+ */
+void omap_ctrl_set_dsp_bootaddr(u32 pa)
+{
+ if (!(cpu_is_omap2430() || cpu_is_omap34xx())) {
+ WARN(1, "control: %s: not supported on this SoC\n", __func__);
+ return;
+ }
+
+ WARN(pa & ~OMAP_CTRL_DSP_BOOTADDR_MASK,
+ "control: %s: invalid DSP boot address %08x\n", __func__, pa);
+
+ omap_ctrl_writel(pa, OMAP243X_CONTROL_IVA2_BOOTADDR);
+}
+
+/**
+ * omap_ctrl_set_dsp_bootmode - set the DSP's boot mode
+ * @mode: DSP boot mode (described below)
+ *
+ * Sets the DSP boot mode - see OMAP3 TRM revision ZH section 7.4.7.4
+ * "IVA2.2 Boot Registers". Known values of @mode include 0, to boot
+ * directly to the address supplied by omap2_ctrl_set_dsp_bootaddr();
+ * 1, to boot to the DSP's ROM code and idle, waiting for interrupts;
+ * 2, to boot to the DSP's ROM code and spin in an idle loop; 3, to
+ * copy the user's bootstrap code from the DSP's internal memory and
+ * execute it (XXX how does the DSP know where to copy from?); and 4,
+ * to execute the DSP ROM code's context restore code. No return
+ * value.
+ */
+void omap_ctrl_set_dsp_bootmode(u8 mode)
+{
+ if (!(cpu_is_omap2430() || cpu_is_omap34xx())) {
+ WARN(1, "control: %s: not supported on this SoC\n", __func__);
+ return;
+ }
+
+ omap_ctrl_writel(mode, OMAP243X_CONTROL_IVA2_BOOTMOD);
+}
+
+
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
/*
* Clears the scratchpad contents in case of cold boot-
@@ -258,11 +258,6 @@
/* CONTROL_PROG_IO1 bits */
#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
-/* CONTROL_IVA2_BOOTMOD bits */
-#define OMAP3_IVA2_BOOTMOD_SHIFT 0
-#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
-#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
-
/* CONTROL_PADCONF_X bits */
#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
@@ -330,6 +325,8 @@
#define FEAT_NEON 0
#define FEAT_NEON_NONE 1
+/* DSP booting-related constants */
+#define OMAP_CTRL_DSP_BOOTADDR_MASK 0xfffffc00
#ifndef __ASSEMBLY__
#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -351,6 +348,9 @@ extern u32 omap3_arm_context[128];
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
+extern void omap_ctrl_set_dsp_bootaddr(u32 pa);
+extern void omap_ctrl_set_dsp_bootmode(u8 mode);
+
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
@@ -28,4 +28,10 @@ extern void omap_dsp_reserve_sdram_memblock(void);
static inline void omap_dsp_reserve_sdram_memblock(void) { }
#endif
+#define OMAP_DSP_BOOTMODE_USER 0
+#define OMAP_DSP_BOOTMODE_IDLE 1
+#define OMAP_DSP_BOOTMODE_BUSYLOOP 2
+#define OMAP_DSP_BOOTMODE_COPY 3
+#define OMAP_DSP_BOOTMODE_RESTORE 4
+
#endif