From patchwork Tue Nov 16 15:38:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 328412 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oAGFcPem019020 for ; Tue, 16 Nov 2010 15:38:25 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753680Ab0KPPiX (ORCPT ); Tue, 16 Nov 2010 10:38:23 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:45837 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753436Ab0KPPiU (ORCPT ); Tue, 16 Nov 2010 10:38:20 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id oAGFcEZ0003074 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 16 Nov 2010 09:38:17 -0600 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id oAGFc8A7004753; Tue, 16 Nov 2010 21:08:08 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id oAGFc8HN005265; Tue, 16 Nov 2010 21:08:08 +0530 Received: (from a0131687@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id oAGFc8fJ005263; Tue, 16 Nov 2010 21:08:08 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: paul@pwsan.com, b-cousson@ti.com, khilman@deeprootsystems.com, Rajendra Nayak Subject: [PATCH 4/6] OMAP: powerdomain: Arch specific funcs for logic control Date: Tue, 16 Nov 2010 21:08:04 +0530 Message-Id: <1289921886-5139-5-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1289921886-5139-4-git-send-email-rnayak@ti.com> References: <1289921886-5139-1-git-send-email-rnayak@ti.com> <1289921886-5139-2-git-send-email-rnayak@ti.com> <1289921886-5139-3-git-send-email-rnayak@ti.com> <1289921886-5139-4-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Tue, 16 Nov 2010 15:38:25 +0000 (UTC) diff --git a/arch/arm/mach-omap2/powerdomains2xxx.c b/arch/arm/mach-omap2/powerdomains2xxx.c index dfeb8af..779529d 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx.c +++ b/arch/arm/mach-omap2/powerdomains2xxx.c @@ -45,9 +45,43 @@ static int omap2_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) OMAP3430_LASTPOWERSTATEENTERED_MASK); } +static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) +{ + u32 v; + + v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); + prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + + return 0; +} + +static int omap2_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) +{ + return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, + OMAP3430_LOGICSTATEST_MASK); +} + + +static int omap2_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) +{ + return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, + OMAP3430_LASTLOGICSTATEENTERED_MASK); +} + +static int omap2_pwrdm_read_logic_retst(struct powerdomain *pwrdm) +{ + return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, + OMAP3430_LOGICSTATEST_MASK); +} + struct pwrdm_functions omap2_pwrdm_functions = { .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, .pwrdm_read_prev_pwrst = omap2_pwrdm_read_prev_pwrst, + .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, + .pwrdm_read_logic_pwrst = omap2_pwrdm_read_logic_pwrst, + .pwrdm_read_prev_logic_pwrst = omap2_pwrdm_read_prev_logic_pwrst, + .pwrdm_read_logic_retst = omap2_pwrdm_read_logic_retst, }; diff --git a/arch/arm/mach-omap2/powerdomains44xx.c b/arch/arm/mach-omap2/powerdomains44xx.c index b3aaf9b..016a425 100644 --- a/arch/arm/mach-omap2/powerdomains44xx.c +++ b/arch/arm/mach-omap2/powerdomains44xx.c @@ -45,9 +45,35 @@ static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) OMAP4430_LASTPOWERSTATEENTERED_MASK); } +static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) +{ + u32 v; + + v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); + prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, + pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); + + return 0; +} + +static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) +{ + return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, + OMAP4430_LOGICSTATEST_MASK); +} + +static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) +{ + return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, + OMAP4430_LOGICRETSTATE_MASK); +} + struct pwrdm_functions omap4_pwrdm_functions = { .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst, .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst, + .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst, + .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst, + .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst, }; diff --git a/arch/arm/plat-omap/powerdomain.c b/arch/arm/plat-omap/powerdomain.c index 73d6dad..9177fbb 100644 --- a/arch/arm/plat-omap/powerdomain.c +++ b/arch/arm/plat-omap/powerdomain.c @@ -531,7 +531,7 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) */ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) { - u32 v; + int ret = -EINVAL; if (!pwrdm) return -EINVAL; @@ -542,17 +542,10 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n", pwrdm->name, pwrst); - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); - prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, - pwrdm->prcm_offs, pwrstctrl_reg_offs); + if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst) + ret = arch_pwrdm->pwrdm_set_logic_retst(pwrdm, pwrst); - return 0; + return ret; } /** @@ -695,11 +688,15 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) */ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstst_reg_offs, - OMAP3430_LOGICSTATEST_MASK); + if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_pwrst) + ret = arch_pwrdm->pwrdm_read_logic_pwrst(pwrdm); + + return ret; } /** @@ -712,17 +709,15 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) */ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, - OMAP3430_LASTLOGICSTATEENTERED_MASK); + if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_logic_pwrst) + ret = arch_pwrdm->pwrdm_read_prev_logic_pwrst(pwrdm); + + return ret; } /** @@ -735,17 +730,15 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) */ int pwrdm_read_logic_retst(struct powerdomain *pwrdm) { + int ret = -EINVAL; + if (!pwrdm) return -EINVAL; - /* - * The register bit names below may not correspond to the - * actual names of the bits in each powerdomain's register, - * but the type of value returned is the same for each - * powerdomain. - */ - return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs, - OMAP3430_LOGICSTATEST_MASK); + if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_retst) + ret = arch_pwrdm->pwrdm_read_logic_retst(pwrdm); + + return ret; } /**