From patchwork Thu Dec 2 11:27:13 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 374141 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB2BRknI019123 for ; Thu, 2 Dec 2010 11:27:46 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757493Ab0LBL1p (ORCPT ); Thu, 2 Dec 2010 06:27:45 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:43279 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755394Ab0LBL1o (ORCPT ); Thu, 2 Dec 2010 06:27:44 -0500 Received: from dlep34.itg.ti.com ([157.170.170.115]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id oB2BRgLj027256 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 2 Dec 2010 05:27:42 -0600 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id oB2BReid002606; Thu, 2 Dec 2010 05:27:40 -0600 (CST) Received: from localhost (ubna0393844.apr.dhcp.ti.com [172.24.137.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id oB2BRcf17225; Thu, 2 Dec 2010 05:27:39 -0600 (CST) From: Archit Taneja To: tomi.valkeinen@nokia.com Cc: linux-omap@vger.kernel.org, Archit Taneja Subject: [PATCH v6 6/7] OMAP: DSS2: Use dss_features to handle DISPC bits removed on OMAP4 Date: Thu, 2 Dec 2010 16:57:13 +0530 Message-Id: <1291289235-12122-7-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1291289235-12122-1-git-send-email-archit@ti.com> References: <1291289235-12122-1-git-send-email-archit@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Thu, 02 Dec 2010 11:27:46 +0000 (UTC) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index fe41d89..6171bcc 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -1922,6 +1922,9 @@ void dispc_enable_channel(enum omap_channel channel, bool enable) void dispc_lcd_enable_signal_polarity(bool act_high) { + if (!dss_has_feature(FEAT_LCDENABLEPOL)) + return; + enable_clocks(1); REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); enable_clocks(0); @@ -1929,6 +1932,9 @@ void dispc_lcd_enable_signal_polarity(bool act_high) void dispc_lcd_enable_signal(bool enable) { + if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) + return; + enable_clocks(1); REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); enable_clocks(0); @@ -1936,6 +1942,9 @@ void dispc_lcd_enable_signal(bool enable) void dispc_pck_free_enable(bool enable) { + if (!dss_has_feature(FEAT_PCKFREEENABLE)) + return; + enable_clocks(1); REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); enable_clocks(0); @@ -3246,7 +3255,8 @@ static void _omap_dispc_initial_config(void) dispc_write_reg(DISPC_SYSCONFIG, l); /* FUNCGATED */ - REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); + if (dss_has_feature(FEAT_FUNCGATED)) + REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); /* L3 firewall setting: enable access to OCM RAM */ /* XXX this should be somewhere in plat-omap */