From patchwork Fri Dec 3 17:03:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 378591 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB3H3nSi009215 for ; Fri, 3 Dec 2010 17:03:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752325Ab0LCRDs (ORCPT ); Fri, 3 Dec 2010 12:03:48 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:44348 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752314Ab0LCRDq (ORCPT ); Fri, 3 Dec 2010 12:03:46 -0500 Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id oB3H3j6X029965 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 3 Dec 2010 11:03:45 -0600 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id oB3H3gd2006375; Fri, 3 Dec 2010 11:03:42 -0600 (CST) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id oB3H3gf11542; Fri, 3 Dec 2010 11:03:42 -0600 (CST) Received: by senorita (Postfix, from userid 1000) id DD2BFC24A; Fri, 3 Dec 2010 11:03:41 -0600 (CST) From: Nishanth Menon To: linux-omap Cc: Nishanth Menon , Kevin Hilman , Tony Lindgren , Ambresh K Subject: [PATCH 3/5 v3] OMAP3630: PM: Erratum i608: disable RTA Date: Fri, 3 Dec 2010 11:03:36 -0600 Message-Id: <1291395818-8639-4-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1291395818-8639-1-git-send-email-nm@ti.com> References: <1291395818-8639-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 03 Dec 2010 17:03:50 +0000 (UTC) diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 1fa3294..728f268 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void) /* Populate the Scratchpad contents */ scratchpad_contents.boot_config_ptr = 0x0; - if (omap_rev() != OMAP3430_REV_ES3_0 && + if (cpu_is_omap3630()) + scratchpad_contents.public_restore_ptr = + virt_to_phys(get_omap3630_restore_pointer()); + else if (omap_rev() != OMAP3430_REV_ES3_0 && omap_rev() != OMAP3430_REV_ES3_1) scratchpad_contents.public_restore_ptr = virt_to_phys(get_restore_pointer()); diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index b6c6b7c..d7911c5 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -204,6 +204,10 @@ #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) +/* 36xx-only RTA - Retention till Accesss control registers and bits */ +#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C +#define OMAP36XX_RTA_DISABLE 0x0 + /* 34xx D2D idle-related pins, handled by PM core */ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 @@ -347,6 +351,7 @@ extern void omap3_save_scratchpad_contents(void); extern void omap3_clear_scratchpad_contents(void); extern u32 *get_restore_pointer(void); extern u32 *get_es3_restore_pointer(void); +extern u32 *get_omap3630_restore_pointer(void); extern u32 omap3_arm_context[128]; extern void omap3_control_save_context(void); extern void omap3_control_restore_context(void); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 0ec8a04..a89ffc7 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -55,6 +55,10 @@ #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 +#define RTA_ERRATUM_i608 (1 << 0) +static u16 pm34xx_errata; +#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id)) + struct power_state { struct powerdomain *pwrdm; u32 next_state; @@ -989,6 +993,12 @@ void omap_push_sram_idle(void) save_secure_ram_context_sz); } +static void __init pm_errata_configure(void) +{ + if (cpu_is_omap3630()) + pm34xx_errata |= RTA_ERRATUM_i608; +} + static int __init omap3_pm_init(void) { struct power_state *pwrst, *tmp; @@ -998,6 +1008,8 @@ static int __init omap3_pm_init(void) if (!cpu_is_omap34xx()) return -ENODEV; + pm_errata_configure(); + printk(KERN_ERR "Power Management for TI OMAP3.\n"); /* XXX prcm_setup_regs needs to be before enabling hw @@ -1045,6 +1057,15 @@ static int __init omap3_pm_init(void) pm_idle = omap3_pm_idle; omap3_idle_init(); + /* + * RTA is disabled during initialization as per erratum i608 + * it is safer to disable rta by the bootloader, but we would like + * to be doubly sure here and prevent any mishaps. + */ + if (IS_PM34XX_ERRATUM(RTA_ERRATUM_i608)) + omap_ctrl_writel(OMAP36XX_RTA_DISABLE, + OMAP36XX_CONTROL_MEM_RTA_CTRL); + clkdm_add_wkdep(neon_clkdm, mpu_clkdm); if (omap_type() != OMAP2_DEVICE_TYPE_GP) { omap3_secure_ram_storage = diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 3fbd1e5..cc3507b 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -45,6 +45,8 @@ #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) #define SRAM_BASE_P 0x40200000 #define CONTROL_STAT 0x480022F0 +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\ + + OMAP36XX_CONTROL_MEM_RTA_CTRL) #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is * available */ #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\ @@ -99,6 +101,14 @@ ENTRY(get_restore_pointer) ldmfd sp!, {pc} @ restore regs and return ENTRY(get_restore_pointer_sz) .word . - get_restore_pointer + .text +/* Function call to get the restore pointer for 3630 resume from OFF */ +ENTRY(get_omap3630_restore_pointer) + stmfd sp!, {lr} @ save registers on stack + adr r0, restore_3630 + ldmfd sp!, {pc} @ restore regs and return +ENTRY(get_omap3630_restore_pointer_sz) + .word . - get_omap3630_restore_pointer .text /* Function call to get the restore pointer for for ES3 to resume from OFF */ @@ -246,6 +256,20 @@ copy_to_sram: bne copy_to_sram ldr r1, sram_base blx r1 + b restore + +restore_3630: + /*b restore_es3630*/ @ Enable to debug restore code + ldr r1, pm_prepwstst_core_p + ldr r2, [r1] + and r2, r2, #0x3 + cmp r2, #0x0 @ Check if previous power state of CORE is OFF + bne restore + /* Disable rta before giving control */ + ldr r1, control_mem_rta + mov r2, #OMAP36XX_RTA_DISABLE + str r2, [r1] + /* Fall thru for the remaining logic */ restore: /* b restore*/ @ Enable to debug restore code /* Check what was the reason for mpu reset and store the reason in r9*/ @@ -650,6 +674,8 @@ cache_pred_disable_mask: .word 0xFFFFE7FB control_stat: .word CONTROL_STAT +control_mem_rta: + .word CONTROL_MEM_RTA_CTRL kernel_flush: .word v7_flush_dcache_all /* these 2 words need to be at the end !!! */