From patchwork Mon Dec 6 08:13:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar Gupta X-Patchwork-Id: 377322 X-Patchwork-Delegate: me@felipebalbi.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB68Dgep031338 for ; Mon, 6 Dec 2010 08:13:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751332Ab0LFINh (ORCPT ); Mon, 6 Dec 2010 03:13:37 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:53437 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750964Ab0LFINh (ORCPT ); Mon, 6 Dec 2010 03:13:37 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id oB68DXwp013806 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 6 Dec 2010 02:13:35 -0600 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id oB68DV7B006636; Mon, 6 Dec 2010 13:43:32 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id oB68DVL2000995; Mon, 6 Dec 2010 13:43:31 +0530 Received: (from a0393629@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id oB68DVQA000992; Mon, 6 Dec 2010 13:43:31 +0530 From: Ajay Kumar Gupta To: linux-usb@vger.kernel.org Cc: linux-omap@vger.kernel.org, balbi@ti.com, Ajay Kumar Gupta Subject: [PATCH v2] musb: am35x: fix compile error due to control apis Date: Mon, 6 Dec 2010 13:43:31 +0530 Message-Id: <1291623211-959-1-git-send-email-ajay.gupta@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Mon, 06 Dec 2010 08:13:43 +0000 (UTC) diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 7260558..8c1d121 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -30,9 +30,102 @@ #include #include #include +#include "control.h" #ifdef CONFIG_USB_MUSB_SOC +static void am35x_musb_reset(void) +{ + u32 regval; + + /* Reset the musb interface */ + regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + + regval |= AM35XX_USBOTGSS_SW_RST; + omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); + + regval &= ~AM35XX_USBOTGSS_SW_RST; + omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); + + regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); +} + +static void am35x_musb_phy_power(u8 on) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(100); + u32 devconf2; + + if (on) { + /* + * Start the on-chip PHY and its PLL. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); + devconf2 |= CONF2_PHY_PLLON; + + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + + pr_info(KERN_INFO "Waiting for PHY clock good...\n"); + while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) + & CONF2_PHYCLKGD)) { + cpu_relax(); + + if (time_after(jiffies, timeout)) { + pr_err(KERN_ERR "musb PHY clock good timed out\n"); + break; + } + } + } else { + /* + * Power down the on-chip PHY. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~CONF2_PHY_PLLON; + devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + } +} + +static void am35x_musb_clear_irq(void) +{ + u32 regval; + + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + regval |= AM35XX_USBOTGSS_INT_CLR; + omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); +} + +static void am35x_musb_set_mode(u8 musb_mode) +{ + u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~CONF2_OTGMODE; + switch (musb_mode) { +#ifdef CONFIG_USB_MUSB_HDRC_HCD + case MUSB_HOST: /* Force VBUS valid, ID = 0 */ + devconf2 |= CONF2_FORCE_HOST; + break; +#endif +#ifdef CONFIG_USB_GADGET_MUSB_HDRC + case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ + devconf2 |= CONF2_FORCE_DEVICE; + break; +#endif +#ifdef CONFIG_USB_MUSB_OTG + case MUSB_OTG: /* Don't override the VBUS/ID comparators */ + devconf2 |= CONF2_NO_OVERRIDE; + break; +#endif + default: + pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); + } + + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); +} + static struct resource musb_resources[] = { [0] = { /* start and end set dynamically */ .flags = IORESOURCE_MEM, @@ -93,6 +186,10 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) } else if (cpu_is_omap3517() || cpu_is_omap3505()) { musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; musb_resources[1].start = INT_35XX_USBOTG_IRQ; + board_data->set_phy_power = am35x_musb_phy_power; + board_data->clear_irq = am35x_musb_clear_irq; + board_data->set_mode = am35x_musb_set_mode; + board_data->reset = am35x_musb_reset; } else if (cpu_is_omap34xx()) { musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; } else if (cpu_is_omap44xx()) { diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 59c7fe7..7c0be5a 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -69,6 +69,10 @@ struct omap_musb_board_data { u8 mode; u16 power; unsigned extvbus:1; + void (*set_phy_power)(u8 on); + void (*clear_irq)(void); + void (*set_mode)(u8 mode); + void (*reset)(void); }; enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c index b0aabf3..5ac1c51 100644 --- a/drivers/usb/musb/am35x.c +++ b/drivers/usb/musb/am35x.c @@ -30,7 +30,6 @@ #include #include -#include #include #include "musb_core.h" @@ -80,47 +79,6 @@ #define USB_MENTOR_CORE_OFFSET 0x400 -static inline void phy_on(void) -{ - unsigned long timeout = jiffies + msecs_to_jiffies(100); - u32 devconf2; - - /* - * Start the on-chip PHY and its PLL. - */ - devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); - - devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); - devconf2 |= CONF2_PHY_PLLON; - - omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); - - DBG(1, "Waiting for PHY clock good...\n"); - while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) - & CONF2_PHYCLKGD)) { - cpu_relax(); - - if (time_after(jiffies, timeout)) { - DBG(1, "musb PHY clock good timed out\n"); - break; - } - } -} - -static inline void phy_off(void) -{ - u32 devconf2; - - /* - * Power down the on-chip PHY. - */ - devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); - - devconf2 &= ~CONF2_PHY_PLLON; - devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; - omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); -} - /* * musb_platform_enable - enable interrupts */ @@ -255,9 +213,12 @@ static irqreturn_t am35x_interrupt(int irq, void *hci) { struct musb *musb = hci; void __iomem *reg_base = musb->ctrl_base; + struct device *dev = musb->controller; + struct musb_hdrc_platform_data *plat = dev->platform_data; + struct omap_musb_board_data *data = plat->board_data; unsigned long flags; irqreturn_t ret = IRQ_NONE; - u32 epintr, usbintr, lvl_intr; + u32 epintr, usbintr; spin_lock_irqsave(&musb->lock, flags); @@ -346,9 +307,8 @@ eoi: /* EOI needs to be written for the IRQ to be re-asserted. */ if (ret == IRQ_HANDLED || epintr || usbintr) { /* clear level interrupt */ - lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); - lvl_intr |= AM35XX_USBOTGSS_INT_CLR; - omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR); + if (data->clear_irq) + data->clear_irq(); /* write EOI */ musb_writel(reg_base, USB_END_OF_INTR_REG, 0); } @@ -364,37 +324,24 @@ eoi: int musb_platform_set_mode(struct musb *musb, u8 musb_mode) { - u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + struct device *dev = musb->controller; + struct musb_hdrc_platform_data *plat = dev->platform_data; + struct omap_musb_board_data *data = plat->board_data; + int retval = 0; - devconf2 &= ~CONF2_OTGMODE; - switch (musb_mode) { -#ifdef CONFIG_USB_MUSB_HDRC_HCD - case MUSB_HOST: /* Force VBUS valid, ID = 0 */ - devconf2 |= CONF2_FORCE_HOST; - break; -#endif -#ifdef CONFIG_USB_GADGET_MUSB_HDRC - case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ - devconf2 |= CONF2_FORCE_DEVICE; - break; -#endif -#ifdef CONFIG_USB_MUSB_OTG - case MUSB_OTG: /* Don't override the VBUS/ID comparators */ - devconf2 |= CONF2_NO_OVERRIDE; - break; -#endif - default: - DBG(2, "Trying to set unsupported mode %u\n", musb_mode); - } + if (data->set_mode) + data->set_mode(musb_mode); + else + retval = -EIO; - omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); - return 0; + return retval; } int __init musb_platform_init(struct musb *musb, void *board_data) { + struct omap_musb_board_data *data = board_data; void __iomem *reg_base = musb->ctrl_base; - u32 rev, lvl_intr, sw_reset; + u32 rev; int status; musb->mregs += USB_MENTOR_CORE_OFFSET; @@ -429,29 +376,22 @@ int __init musb_platform_init(struct musb *musb, void *board_data) musb->board_set_vbus = am35x_set_vbus; - /* Global reset */ - sw_reset = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); - - sw_reset |= AM35XX_USBOTGSS_SW_RST; - omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET); - - sw_reset &= ~AM35XX_USBOTGSS_SW_RST; - omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET); - - /* Reset the controller */ - musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); + /* Start the on-chip PHY and its PLL. */ + if (data->reset) + data->reset(); /* Start the on-chip PHY and its PLL. */ - phy_on(); + if (data->set_phy_power) + data->set_phy_power(1); msleep(5); musb->isr = am35x_interrupt; /* clear level interrupt */ - lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); - lvl_intr |= AM35XX_USBOTGSS_INT_CLR; - omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR); + if (data->clear_irq) + data->clear_irq(); + return 0; exit1: clk_disable(musb->phy_clock); @@ -463,10 +403,16 @@ exit0: int musb_platform_exit(struct musb *musb) { + struct device *dev = musb->controller; + struct musb_hdrc_platform_data *plat = dev->platform_data; + struct omap_musb_board_data *data = plat->board_data; + if (is_host_enabled(musb)) del_timer_sync(&otg_workaround); - phy_off(); + /* Shutdown the on-chip PHY and its PLL. */ + if (data->set_phy_power) + data->set_phy_power(0); otg_put_transceiver(musb->xceiv); usb_nop_xceiv_unregister(); @@ -483,13 +429,25 @@ int musb_platform_exit(struct musb *musb) void musb_platform_save_context(struct musb *musb, struct musb_context_registers *musb_context) { - phy_off(); + struct device *dev = musb->controller; + struct musb_hdrc_platform_data *plat = dev->platform_data; + struct omap_musb_board_data *data = plat->board_data; + + /* Shutdown the on-chip PHY and its PLL. */ + if (data->set_phy_power) + data->set_phy_power(0); } void musb_platform_restore_context(struct musb *musb, struct musb_context_registers *musb_context) { - phy_on(); + struct device *dev = musb->controller; + struct musb_hdrc_platform_data *plat = dev->platform_data; + struct omap_musb_board_data *data = plat->board_data; + + /* Start the on-chip PHY and its PLL. */ + if (data->set_phy_power) + data->set_phy_power(1); } #endif