From patchwork Thu Dec 9 22:13:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 396632 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB9ME9N5026341 for ; Thu, 9 Dec 2010 22:14:14 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757434Ab0LIWON (ORCPT ); Thu, 9 Dec 2010 17:14:13 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:48592 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757401Ab0LIWOK (ORCPT ); Thu, 9 Dec 2010 17:14:10 -0500 Received: from dlep34.itg.ti.com ([157.170.170.115]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id oB9ME2Bv002226 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 9 Dec 2010 16:14:02 -0600 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id oB9ME2Cr001178; Thu, 9 Dec 2010 16:14:02 -0600 (CST) Received: from dlee73.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id oB9ME24q003343; Thu, 9 Dec 2010 16:14:02 -0600 (CST) Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE73.ent.ti.com (157.170.170.88) with Microsoft SMTP Server id 8.3.106.1; Thu, 9 Dec 2010 16:14:01 -0600 Received: from localhost.localdomain (lncpu04.tif.ti.com [137.167.102.15]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id oB9MDhZl015306; Thu, 9 Dec 2010 16:14:00 -0600 From: Benoit Cousson To: , CC: , , Rajendra Nayak , Benoit Cousson Subject: [PATCH v2 6/8] OMAP4: clock data: Add SCRM auxiliary clock nodes Date: Thu, 9 Dec 2010 23:13:38 +0100 Message-ID: <1291932820-11163-7-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1291932820-11163-1-git-send-email-b-cousson@ti.com> References: <1291932820-11163-1-git-send-email-b-cousson@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Thu, 09 Dec 2010 22:14:14 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 6558d91..fd7efe8 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -35,6 +35,7 @@ #include "prm.h" #include "prm-regbits-44xx.h" #include "control.h" +#include "scrm44xx.h" /* Root clocks */ @@ -2822,6 +2823,168 @@ static struct clk trace_clk_div_ck = { .set_rate = &omap2_clksel_set_rate, }; +/* SCRM aux clk nodes */ + +static const struct clksel auxclk_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static struct clk auxclk0_ck = { + .name = "auxclk0_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK0, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK0, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; + +static struct clk auxclk1_ck = { + .name = "auxclk1_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK1, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK1, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; + +static struct clk auxclk2_ck = { + .name = "auxclk2_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK2, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK2, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; +static struct clk auxclk3_ck = { + .name = "auxclk3_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK3, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK3, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; + +static struct clk auxclk4_ck = { + .name = "auxclk4_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK4, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK4, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; + +static struct clk auxclk5_ck = { + .name = "auxclk5_ck", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_omap2_dflt, + .clksel = auxclk_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK5, + .clksel_mask = OMAP4_SRCSELECT_MASK, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4_SCRM_AUXCLK5, + .enable_bit = OMAP4_ENABLE_SHIFT, +}; + +static const struct clksel auxclkreq_sel[] = { + { .parent = &auxclk0_ck, .rates = div_1_0_rates }, + { .parent = &auxclk1_ck, .rates = div_1_1_rates }, + { .parent = &auxclk2_ck, .rates = div_1_2_rates }, + { .parent = &auxclk3_ck, .rates = div_1_3_rates }, + { .parent = &auxclk4_ck, .rates = div_1_4_rates }, + { .parent = &auxclk5_ck, .rates = div_1_5_rates }, + { .parent = NULL }, +}; + +static struct clk auxclkreq0_ck = { + .name = "auxclkreq0_ck", + .parent = &auxclk0_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ0, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk auxclkreq1_ck = { + .name = "auxclkreq1_ck", + .parent = &auxclk1_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ1, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk auxclkreq2_ck = { + .name = "auxclkreq2_ck", + .parent = &auxclk2_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ2, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk auxclkreq3_ck = { + .name = "auxclkreq3_ck", + .parent = &auxclk3_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ3, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk auxclkreq4_ck = { + .name = "auxclkreq4_ck", + .parent = &auxclk4_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ4, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk auxclkreq5_ck = { + .name = "auxclkreq5_ck", + .parent = &auxclk5_ck, + .init = &omap2_init_clksel_parent, + .ops = &clkops_null, + .clksel = auxclkreq_sel, + .clksel_reg = OMAP4_SCRM_AUXCLKREQ5, + .clksel_mask = OMAP4_MAPPING_MASK, + .recalc = &omap2_clksel_recalc, +}; + /* * clkdev */ @@ -3078,6 +3241,18 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), CLK("omap_wdt", "ick", &dummy_ck, CK_443X), + CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), + CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), + CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), + CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), + CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), + CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), + CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), + CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), + CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), + CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), + CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), + CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), }; int __init omap4xxx_clk_init(void)