From patchwork Tue Dec 14 13:31:39 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 409881 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBEDVqXe028758 for ; Tue, 14 Dec 2010 13:31:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756285Ab0LNNbt (ORCPT ); Tue, 14 Dec 2010 08:31:49 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:48210 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755305Ab0LNNbs (ORCPT ); Tue, 14 Dec 2010 08:31:48 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id oBEDVhJY008106 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 14 Dec 2010 07:31:45 -0600 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id oBEDVeVF004393; Tue, 14 Dec 2010 19:01:41 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id oBEDVeHY011408; Tue, 14 Dec 2010 19:01:40 +0530 Received: (from a0131687@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id oBEDVdgF011405; Tue, 14 Dec 2010 19:01:39 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: Rajendra Nayak , Kevin Hilman , Paul Walmsley Subject: [PATCH] OMAP3: PM: Fix CLK_SRC mask for IVA2 and MPU Date: Tue, 14 Dec 2010 19:01:39 +0530 Message-Id: <1292333499-11352-1-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.6.6 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Tue, 14 Dec 2010 13:31:53 +0000 (UTC) diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 4f959a7..d5c8fb6 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -81,7 +81,7 @@ /* CM_CLKSEL1_PLL_IVA2 */ #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 -#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) +#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 @@ -126,7 +126,7 @@ /* CM_CLKSEL1_PLL_MPU */ #define OMAP3430_MPU_CLK_SRC_SHIFT 19 -#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) +#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_MPU_DPLL_DIV_SHIFT 0