@@ -153,7 +153,11 @@ static void sr_set_clk_length(struct omap_sr *sr)
struct clk *sys_ck;
u32 sys_clk_speed;
- sys_ck = clk_get(NULL, "sys_ck");
+ if (cpu_is_omap34xx())
+ sys_ck = clk_get(NULL, "sys_ck");
+ else
+ sys_ck = clk_get(NULL, "sys_clkin_ck");
+
if (IS_ERR(sys_ck)) {
dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
__func__);
@@ -193,7 +197,7 @@ static void sr_set_regfields(struct omap_sr *sr)
* file or pmic specific data structure. In that case these structure
* fields will have to be populated using the pdata or pmic structure.
*/
- if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
sr->err_weight = OMAP3430_SR_ERRWEIGHT;
sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
sr->accum_data = OMAP3430_SR_ACCUMDATA;
@@ -20,6 +20,7 @@
#include <linux/err.h>
#include <linux/slab.h>
+#include <linux/io.h>
#include <plat/omap_device.h>
#include <plat/smartreflex.h>
@@ -51,7 +52,21 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
GFP_KERNEL);
for (i = 0; i < count; i++) {
- u32 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+ u32 v;
+ /*
+ * In OMAP4 the efuse registers are 24 bit aligned.
+ * A __raw_readl will fail for non-32 bit aligned address
+ * and hence the 8-bit read and shift.
+ */
+ if (cpu_is_omap44xx()) {
+ u16 offset = volt_data[i].sr_efuse_offs;
+
+ v = omap_ctrl_readb(offset) |
+ omap_ctrl_readb(offset + 1) << 8 |
+ omap_ctrl_readb(offset + 2) << 16;
+ } else {
+ v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+ }
nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
nvalue_table[i].nvalue = v;
@@ -37,7 +37,7 @@ config OMAP_DEBUG_LEDS
config OMAP_SMARTREFLEX
bool "SmartReflex support"
- depends on ARCH_OMAP3 && PM
+ depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
help
Say Y if you want to enable SmartReflex.