From patchwork Mon Dec 20 20:05:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 422301 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBL0RA9H011307 for ; Tue, 21 Dec 2010 00:31:12 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933146Ab0LTUFb (ORCPT ); Mon, 20 Dec 2010 15:05:31 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:49957 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933142Ab0LTUF2 (ORCPT ); Mon, 20 Dec 2010 15:05:28 -0500 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id oBKK5BqD021022 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 20 Dec 2010 14:05:12 -0600 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id oBKK5BbO025956; Mon, 20 Dec 2010 14:05:11 -0600 (CST) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id oBKK5Af05944; Mon, 20 Dec 2010 14:05:11 -0600 (CST) Received: by senorita (Postfix, from userid 1000) id 673CBC2B3; Mon, 20 Dec 2010 14:05:09 -0600 (CST) From: Nishanth Menon To: linux-omap , linux-arm Cc: Jean Pihet , Kevin , Tony , Santosh Subject: [PATCH v5 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache Date: Mon, 20 Dec 2010 14:05:07 -0600 Message-Id: <1292875509-9896-6-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1292875509-9896-1-git-send-email-nm@ti.com> References: <1292875509-9896-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Tue, 21 Dec 2010 00:31:12 +0000 (UTC) diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 8d9aa3e..5e0bee9 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz; #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) extern u16 pm34xx_errata; #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id)) +extern void enable_omap3630_toggle_l2_on_restore(void); #else #define IS_PM34XX_ERRATUM(id) 0 +static inline void enable_omap3630_toggle_l2_on_restore(void) { } #endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ #endif diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index a404387..feb1bd9 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -1007,8 +1007,11 @@ void omap_push_sram_idle(void) static void __init pm_errata_configure(void) { - if (cpu_is_omap3630()) + if (cpu_is_omap3630()) { pm34xx_errata |= PM_RTA_ERRATUM_i608; + /* Enable the l2 cache toggling in sleep logic */ + enable_omap3630_toggle_l2_on_restore(); + } } static int __init omap3_pm_init(void) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 4abf447..50887c7 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz) .word . - get_omap3630_restore_pointer .text +/* + * L2 cache needs to be toggled for stable OFF mode functionality on 3630. + * This function sets up a fflag that will allow for this toggling to take + * place on 3630. Hopefully some version in the future maynot need this + */ +ENTRY(enable_omap3630_toggle_l2_on_restore) + stmfd sp!, {lr} @ save registers on stack + /* Setup so that we will disable and enable l2 */ + mov r1, #0x1 + str r1, l2dis_3630 + ldmfd sp!, {pc} @ restore regs and return + + .text /* Function call to get the restore pointer for for ES3 to resume from OFF */ ENTRY(get_es3_restore_pointer) stmfd sp!, {lr} @ save registers on stack @@ -283,6 +296,14 @@ restore: moveq r9, #0x3 @ MPU OFF => L1 and L2 lost movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation bne logic_l1_restore + + ldr r0, l2dis_3630 + cmp r0, #0x1 @ should we disable L2 on 3630? + bne skipl2dis + mrc p15, 0, r0, c1, c0, 1 + bic r0, r0, #2 @ disable L2 cache + mcr p15, 0, r0, c1, c0, 1 +skipl2dis: ldr r0, control_stat ldr r1, [r0] and r1, #0x700 @@ -343,6 +364,13 @@ smi: .word 0xE1600070 @ Call SMI monitor (smieq) mov r12, #0x2 .word 0xE1600070 @ Call SMI monitor (smieq) logic_l1_restore: + ldr r1, l2dis_3630 + cmp r1, #0x1 @ Do we need to re-enable L2 on 3630? + bne skipl2reen + mrc p15, 0, r1, c1, c0, 1 + orr r1, r1, #2 @ re-enable L2 cache + mcr p15, 0, r1, c1, c0, 1 +skipl2reen: mov r1, #0 /* Invalidate all instruction caches to PoU * and flush branch target cache */ @@ -679,6 +707,8 @@ control_mem_rta: .word CONTROL_MEM_RTA_CTRL kernel_flush: .word v7_flush_dcache_all +l2dis_3630: + .word 0 /* * When exporting to userspace while the counters are in SRAM, * these 2 words need to be at the end to facilitate retrival!