From patchwork Tue Dec 21 17:56:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Gamari X-Patchwork-Id: 424791 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBLHul10014324 for ; Tue, 21 Dec 2010 17:56:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752323Ab0LUR4q (ORCPT ); Tue, 21 Dec 2010 12:56:46 -0500 Received: from mail-vw0-f46.google.com ([209.85.212.46]:48541 "EHLO mail-vw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751736Ab0LUR4p (ORCPT ); Tue, 21 Dec 2010 12:56:45 -0500 Received: by vws16 with SMTP id 16so1814897vws.19 for ; Tue, 21 Dec 2010 09:56:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=uZX6gXUQzFKpYtKzWz0Gp2vZVFrdrN3dIbPVzOfHidM=; b=w4fIsYan82MTFeRUbs8ApuLDGedQgQutBvW/531NHGmDeBd8LxFLVJ5CSel71vr53Q jt9aCDlzmG1PS+2U+ck/93OndNItF4eO2+Ku4Vn8jRIySufPHwB6ATSbv1qhwJVRFuvS UvXUXK1kTeiYfjRMvFUb5NEDRxOSBYj/L/FAs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Q544V67ss08mNwE4R4cMdaiZB2i1LJYkmXmEmp5k3PT/re7hbv7mJZ3I+tSJXdrmyw P8T8TPVNq/JI9/vhbqwDSCRJ7rZbjko9WMuinGmMtWRDD2srfVlcJEMwyBN1EL8WUTlZ HQG+2cQEQegKIOdee60AECIhjonBCc6W5K8t0= Received: by 10.220.180.135 with SMTP id bu7mr1803206vcb.0.1292954205071; Tue, 21 Dec 2010 09:56:45 -0800 (PST) Received: from ben-laptop (c-24-61-223-13.hsd1.nh.comcast.net [24.61.223.13]) by mx.google.com with ESMTPS id c11sm495074vcc.14.2010.12.21.09.56.43 (version=SSLv3 cipher=RC4-MD5); Tue, 21 Dec 2010 09:56:44 -0800 (PST) From: Ben Gamari To: beagleboard , linux-omap , David Brownell , Eric Miao , Michael Hennerich , Grant Likely , spi-devel-general Cc: Ben Gamari Subject: [PATCH] mcspi: Add support for GPIO chip select lines Date: Tue, 21 Dec 2010 12:56:35 -0500 Message-Id: <1292954195-20204-2-git-send-email-bgamari.foss@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1b68c6791001272033q60dd31dbif4de285cd9bac83d@mail.gmail.com> References: <1b68c6791001272033q60dd31dbif4de285cd9bac83d@mail.gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Tue, 21 Dec 2010 17:56:48 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h index 1254e49..ab84b8d 100644 --- a/arch/arm/plat-omap/include/plat/mcspi.h +++ b/arch/arm/plat-omap/include/plat/mcspi.h @@ -1,6 +1,20 @@ #ifndef _OMAP2_MCSPI_H #define _OMAP2_MCSPI_H +/** + * struct omap2_mcspi_csinfo - Chip Select description + * @line: Custom 'identity' of the CS line + * @set_level: Function to set the state of a given CS line + * + * This is to allow use of GPIO lines as CS lines. Allocate and initialize one + * in the machine init code and make spi_board_info.controller_data point to + * it. + */ +struct omap2_mcspi_csinfo { + unsigned line; + void (*set_level)(unsigned line_id, int lvl); +}; + struct omap2_mcspi_platform_config { unsigned short num_cs; }; diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index 2a651e6..92ccbd6 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -35,6 +35,7 @@ #include #include +#include #include #include @@ -235,11 +236,14 @@ static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) { - u32 l; - - l = mcspi_cached_chconf0(spi); - MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); - mcspi_write_chconf0(spi, l); + if (spi->controller_data) { + struct omap2_mcspi_csinfo *csinfo = spi->controller_data; + (*csinfo->set_level)(csinfo->line, cs_active); + } else { + u32 l = mcspi_cached_chconf0(spi); + MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); + mcspi_write_chconf0(spi, l); + } } static void omap2_mcspi_set_master_mode(struct spi_master *master)