From patchwork Fri Dec 31 08:07:58 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 442111 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBV88Cri029225 for ; Fri, 31 Dec 2010 08:08:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751913Ab0LaIIL (ORCPT ); Fri, 31 Dec 2010 03:08:11 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:32938 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751698Ab0LaIIK (ORCPT ); Fri, 31 Dec 2010 03:08:10 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id oBV885C4032505 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 31 Dec 2010 02:08:07 -0600 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id oBV880OX002971; Fri, 31 Dec 2010 13:38:01 +0530 (IST) From: Thara Gopinath To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, paul@pwsan.com, b-cousson@ti.com, vishwanath.bs@ti.com, sawant@ti.com, nm@ti.com, Thara Gopinath Subject: [PATCH] OMAP3: PM: Adding T2 enabling of smartreflex Date: Fri, 31 Dec 2010 13:37:58 +0530 Message-Id: <1293782878-9756-1-git-send-email-thara@ti.com> X-Mailer: git-send-email 1.7.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 31 Dec 2010 08:08:15 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 15f8c6c..a59f36b 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -58,7 +58,9 @@ static bool is_offset_valid; static u8 smps_offset; +#define TWL4030_DCDC_GLOBAL_CFG 0x06 #define REG_SMPS_OFFSET 0xE0 +#define SMARTREFLEX_ENABLE BIT(3) unsigned long twl4030_vsel_to_uv(const u8 vsel) { @@ -256,6 +258,7 @@ int __init omap4_twl_init(void) int __init omap3_twl_init(void) { struct voltagedomain *voltdm; + u8 temp; if (!cpu_is_omap34xx()) return -ENODEV; @@ -267,6 +270,19 @@ int __init omap3_twl_init(void) omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX; } + /* + * The smartreflex bit on twl4030 needs to be enabled by + * default irrespective of whether smartreflex module is + * enabled on the OMAP side or not. This is because without + * this bit enabled the voltage scaling through + * vp forceupdate does not function properly on OMAP3. + */ + twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp, + TWL4030_DCDC_GLOBAL_CFG); + temp |= SMARTREFLEX_ENABLE; + twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp, + TWL4030_DCDC_GLOBAL_CFG); + voltdm = omap_voltage_domain_lookup("mpu"); omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);