From patchwork Wed Jan 5 06:20:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Guzman Lugo, Fernando" X-Patchwork-Id: 452871 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p056LE3b022216 for ; Wed, 5 Jan 2011 06:21:14 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751398Ab1AEGUs (ORCPT ); Wed, 5 Jan 2011 01:20:48 -0500 Received: from na3sys009aog107.obsmtp.com ([74.125.149.197]:41306 "EHLO na3sys009aog107.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751388Ab1AEGUs (ORCPT ); Wed, 5 Jan 2011 01:20:48 -0500 Received: from source ([209.85.161.174]) by na3sys009aob107.postini.com ([74.125.148.12]) with SMTP ID DSNKTSQNv76lW7U6AwvhZK2giGAocBxBAYgX@postini.com; Tue, 04 Jan 2011 22:20:48 PST Received: by mail-gx0-f174.google.com with SMTP id 9so3220160gxk.19 for ; Tue, 04 Jan 2011 22:20:47 -0800 (PST) Received: by 10.151.148.7 with SMTP id a7mr21723572ybo.15.1294208447461; Tue, 04 Jan 2011 22:20:47 -0800 (PST) Received: from localhost.localdomain (cpe-76-187-101-230.tx.res.rr.com [76.187.101.230]) by mx.google.com with ESMTPS id i29sm8683102yha.42.2011.01.04.22.20.43 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 04 Jan 2011 22:20:45 -0800 (PST) From: Fernando Guzman Lugo To: Cc: , , , , , Fernando Guzman Lugo , Felipe Contreras Subject: [PATCH] staging: tidspbridge - configure full L1 MMU range Date: Wed, 5 Jan 2011 00:20:10 -0600 Message-Id: <1294208410-4772-1-git-send-email-fernando.lugo@ti.com> X-Mailer: git-send-email 1.7.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Wed, 05 Jan 2011 06:21:14 +0000 (UTC) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 1be081f..ec96d1e 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -70,6 +70,7 @@ #define MMU_LARGE_PAGE_MASK 0xFFFF0000 #define MMU_SMALL_PAGE_MASK 0xFFFFF000 #define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00 +#define MMU_L1_SIZE 0x4000 #define PAGES_II_LVL_TABLE 512 #define PHYS_TO_PAGE(phys) pfn_to_page((phys) >> PAGE_SHIFT) @@ -786,10 +787,7 @@ static int bridge_dev_create(struct bridge_dev_context pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL); if (pt_attrs != NULL) { - /* Assuming that we use only DSP's memory map - * until 0x4000:0000 , we would need only 1024 - * L1 enties i.e L1 size = 4K */ - pt_attrs->l1_size = 0x1000; + pt_attrs->l1_size = MMU_L1_SIZE; align_size = pt_attrs->l1_size; /* Align sizes are expected to be power of 2 */ /* we like to get aligned on L1 table size */