From patchwork Fri Jan 21 14:01:02 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripathy, Vishwanath" X-Patchwork-Id: 495081 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p0LDvgSX022977 for ; Fri, 21 Jan 2011 13:57:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752799Ab1AUN5s (ORCPT ); Fri, 21 Jan 2011 08:57:48 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:52511 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752764Ab1AUN5r (ORCPT ); Fri, 21 Jan 2011 08:57:47 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id p0LDvglK023398 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 21 Jan 2011 07:57:44 -0600 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p0LDvSPa010507; Fri, 21 Jan 2011 19:27:41 +0530 (IST) From: Vishwanath BS To: linux-omap@vger.kernel.org Cc: patches@linaro.org, Thara Gopinath Subject: [PATCH 10/13] OMAP3: Add voltage dependency table for VDD1. Date: Fri, 21 Jan 2011 19:31:02 +0530 Message-Id: <1295618465-15234-11-git-send-email-vishwanath.bs@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1295618465-15234-1-git-send-email-vishwanath.bs@ti.com> References: <1295618465-15234-1-git-send-email-vishwanath.bs@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 21 Jan 2011 13:57:50 +0000 (UTC) diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 92fe20d..8881c0c 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -191,6 +191,39 @@ static struct omap_volt_data omap44xx_vdd_core_volt_data[] = { VOLT_DATA_DEFINE(0, 0, 0, 0), }; +/* OMAP 3430 MPU Core VDD dependency table */ +static struct omap_vdd_dep_volt omap34xx_vdd1_vdd2_data[] = { + {.main_vdd_volt = OMAP3430_VDD_MPU_OPP1_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP50_UV}, + {.main_vdd_volt = OMAP3430_VDD_MPU_OPP2_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP50_UV}, + {.main_vdd_volt = OMAP3430_VDD_MPU_OPP3_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP100_UV}, + {.main_vdd_volt = OMAP3430_VDD_MPU_OPP4_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP100_UV}, + {.main_vdd_volt = OMAP3430_VDD_MPU_OPP5_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP100_UV}, + {.main_vdd_volt = 0, .dep_vdd_volt = 0}, +}; + +static struct omap_vdd_dep_info omap34xx_vdd1_dep_info[] = { + { + .name = "core", + .dep_table = omap34xx_vdd1_vdd2_data, + }, +}; + +/* OMAP 3630 MPU Core VDD dependency table */ +static struct omap_vdd_dep_volt omap36xx_vdd1_vdd2_data[] = { + {.main_vdd_volt = OMAP3630_VDD_MPU_OPP50_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP50_UV}, + {.main_vdd_volt = OMAP3630_VDD_MPU_OPP100_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV}, + {.main_vdd_volt = OMAP3630_VDD_MPU_OPP120_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV}, + {.main_vdd_volt = OMAP3630_VDD_MPU_OPP1G_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV}, + {.main_vdd_volt = 0, .dep_vdd_volt = 0}, +}; + +static struct omap_vdd_dep_info omap36xx_vdd1_dep_info[] = { + { + .name = "core", + .dep_table = omap36xx_vdd1_vdd2_data, + }, +}; + static struct dentry *voltage_dir; /* Init function pointers */ @@ -696,10 +729,15 @@ static int __init omap3_vdd_data_configure(struct omap_vdd_info *vdd) } if (!strcmp(vdd->voltdm.name, "mpu")) { - if (cpu_is_omap3630()) + if (cpu_is_omap3630()) { vdd->volt_data = omap36xx_vddmpu_volt_data; - else + vdd->dep_vdd_info = omap36xx_vdd1_dep_info; + vdd->nr_dep_vdd = ARRAY_SIZE(omap36xx_vdd1_dep_info); + } else { vdd->volt_data = omap34xx_vddmpu_volt_data; + vdd->dep_vdd_info = omap34xx_vdd1_dep_info; + vdd->nr_dep_vdd = ARRAY_SIZE(omap34xx_vdd1_dep_info); + } vdd->vp_reg.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK; vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET;