From patchwork Mon Jan 24 14:20:57 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 500991 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p0OJh2Wj026265 for ; Mon, 24 Jan 2011 19:45:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751648Ab1AXOV0 (ORCPT ); Mon, 24 Jan 2011 09:21:26 -0500 Received: from mail-ww0-f44.google.com ([74.125.82.44]:44611 "EHLO mail-ww0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751435Ab1AXOV0 (ORCPT ); Mon, 24 Jan 2011 09:21:26 -0500 Received: by wwa36 with SMTP id 36so4334031wwa.1 for ; Mon, 24 Jan 2011 06:21:24 -0800 (PST) Received: by 10.227.157.1 with SMTP id z1mr4471508wbw.23.1295878884210; Mon, 24 Jan 2011 06:21:24 -0800 (PST) Received: from localhost.localdomain ([81.245.18.98]) by mx.google.com with ESMTPS id a50sm5034732wer.18.2011.01.24.06.21.22 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 24 Jan 2011 06:21:23 -0800 (PST) From: jean.pihet@newoldbits.com To: Thomas Renninger , linux-omap@vger.kernel.org Cc: Jean Pihet Subject: [PATCH] perf: add OMAP support for the new power events Date: Mon, 24 Jan 2011 15:20:57 +0100 Message-Id: <1295878857-8983-1-git-send-email-j-pihet@ti.com> X-Mailer: git-send-email 1.7.2.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 24 Jan 2011 19:45:13 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 2a2f152..72af75d 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -22,7 +22,9 @@ #include #include #include +#include +#include #include #include "clockdomain.h" #include @@ -261,6 +263,7 @@ void omap2_clk_disable(struct clk *clk) pr_debug("clock: %s: disabling in hardware\n", clk->name); + trace_clock_disable(clk->name, 0, smp_processor_id()); clk->ops->disable(clk); if (clk->clkdm) @@ -312,6 +315,7 @@ int omap2_clk_enable(struct clk *clk) } } + trace_clock_enable(clk->name, 1, smp_processor_id()); ret = clk->ops->enable(clk); if (ret) { WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret); @@ -349,8 +353,10 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ - if (clk->set_rate) + if (clk->set_rate) { + trace_clock_set_rate(clk->name, rate, smp_processor_id()); ret = clk->set_rate(clk, rate); + } return ret; } diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 8cbbead..7c5e0ee 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include "clockdomain.h" @@ -518,8 +519,14 @@ static void omap3_pm_idle(void) if (omap_irq_pending() || need_resched()) goto out; + trace_power_start(POWER_CSTATE, 1, smp_processor_id()); + trace_cpu_idle(1, smp_processor_id()); + omap_sram_idle(); + trace_power_end(smp_processor_id()); + trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); + out: local_fiq_enable(); local_irq_enable(); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index eaed0df..e1feb50 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -19,12 +19,15 @@ #include #include #include +#include + #include "cm2xxx_3xxx.h" #include "prcm44xx.h" #include "cm44xx.h" #include "prm2xxx_3xxx.h" #include "prm44xx.h" +#include #include #include "powerdomain.h" #include "clockdomain.h" @@ -406,8 +409,11 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) pr_debug("powerdomain: setting next powerstate for %s to %0x\n", pwrdm->name, pwrst); - if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) + if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) { + trace_power_domain_target(pwrdm->name, pwrst, + smp_processor_id()); ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst); + } return ret; }