From patchwork Thu Feb 3 13:56:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghuveer Murthy X-Patchwork-Id: 529371 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p13E2SSP008314 for ; Thu, 3 Feb 2011 14:02:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932167Ab1BCOCa (ORCPT ); Thu, 3 Feb 2011 09:02:30 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:33673 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756424Ab1BCOC2 (ORCPT ); Thu, 3 Feb 2011 09:02:28 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p13E2Haq018810 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 3 Feb 2011 08:02:19 -0600 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p13E2EFh004701; Thu, 3 Feb 2011 19:32:16 +0530 (IST) From: Raghuveer Murthy To: tomba@iki.fi Cc: linux-omap@vger.kernel.org Subject: [PATCH 3/4] OMAP: DSS2: Using dss_features to clean cpu checks for clocks Date: Thu, 3 Feb 2011 19:26:58 +0530 Message-Id: <1296741419-9037-4-git-send-email-raghuveer.murthy@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1296741419-9037-1-git-send-email-raghuveer.murthy@ti.com> References: <1296741419-9037-1-git-send-email-raghuveer.murthy@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 03 Feb 2011 14:02:54 +0000 (UTC) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index add82e6..654f5e6 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -320,8 +320,9 @@ int dss_calc_clock_rates(struct dss_clock_info *cinfo) { unsigned long prate; - if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) || - cinfo->fck_div == 0) + if (cinfo->fck_div > + (dss_has_feature(FEAT_DPLL_FCK_32_DIV) ? 32 : 16) || + cinfo->fck_div == 0) return -EINVAL; prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck)); @@ -336,9 +337,9 @@ int dss_set_clock_div(struct dss_clock_info *cinfo) unsigned long prate; int r; - if (cpu_is_omap34xx()) { + if (dss_has_feature(FEAT_VAR_DPLL_FCK)) { prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck)); - DSSDBG("dpll4_m4 = %ld\n", prate); + DSSDBG("dpll_per_mx parent rate = %ld\n", prate); r = clk_set_rate(dss.dpll_per_mx_ck, prate / cinfo->fck_div); if (r) @@ -354,10 +355,10 @@ int dss_get_clock_div(struct dss_clock_info *cinfo) { cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); - if (cpu_is_omap34xx()) { + if (dss_has_feature(FEAT_VAR_DPLL_FCK)) { unsigned long prate; prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck)); - if (cpu_is_omap3630()) + if (dss_has_feature(FEAT_DPLL_FCK_32_DIV)) cinfo->fck_div = prate / (cinfo->fck); else cinfo->fck_div = prate / (cinfo->fck / 2); @@ -370,7 +371,7 @@ int dss_get_clock_div(struct dss_clock_info *cinfo) unsigned long dss_get_dpll_per_rate(void) { - if (cpu_is_omap34xx()) + if (dss_has_feature(FEAT_VAR_DPLL_FCK)) return clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck)); else return 0; @@ -395,8 +396,9 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck, fck = dss_clk_get_rate(DSS_CLK_FCK); if (req_pck == dss.cache_req_pck && - ((cpu_is_omap34xx() && prate == dss.cache_prate) || - dss.cache_dss_cinfo.fck == fck)) { + ((dss_has_feature(FEAT_VAR_DPLL_FCK) && + prate == dss.cache_prate) || + dss.cache_dss_cinfo.fck == fck)) { DSSDBG("dispc clock info found from cache.\n"); *dss_cinfo = dss.cache_dss_cinfo; *dispc_cinfo = dss.cache_dispc_cinfo; @@ -417,7 +419,7 @@ retry: memset(&best_dss, 0, sizeof(best_dss)); memset(&best_dispc, 0, sizeof(best_dispc)); - if (cpu_is_omap24xx()) { + if (!dss_has_feature(FEAT_VAR_DPLL_FCK)) { struct dispc_clock_info cur_dispc; /* XXX can we change the clock on omap2? */ fck = dss_clk_get_rate(DSS_CLK_FCK); @@ -432,12 +434,13 @@ retry: best_dispc = cur_dispc; goto found; - } else if (cpu_is_omap34xx()) { - for (fck_div = (cpu_is_omap3630() ? 32 : 16); - fck_div > 0; --fck_div) { + } else { + for (fck_div = + (dss_has_feature(FEAT_DPLL_FCK_32_DIV) ? 32 : 16); + fck_div > 0; --fck_div) { struct dispc_clock_info cur_dispc; - if (cpu_is_omap3630()) + if (dss_has_feature(FEAT_DPLL_FCK_32_DIV)) fck = prate / fck_div; else fck = prate / fck_div * 2; @@ -465,8 +468,6 @@ retry: goto found; } } - } else { - BUG(); } found: @@ -650,7 +651,7 @@ fail0: static void dss_exit(void) { - if (cpu_is_omap34xx()) + if (dss_has_feature(FEAT_VAR_DPLL_FCK)) clk_put(dss.dpll_per_mx_ck); free_irq(dss.irq, NULL);