From patchwork Thu Feb 3 18:02:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot for Dave Martin X-Patchwork-Id: 530241 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p13I3vfb020127 for ; Thu, 3 Feb 2011 18:03:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756702Ab1BCSD4 (ORCPT ); Thu, 3 Feb 2011 13:03:56 -0500 Received: from mail-wy0-f174.google.com ([74.125.82.174]:52235 "EHLO mail-wy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756682Ab1BCSD4 (ORCPT ); Thu, 3 Feb 2011 13:03:56 -0500 Received: by wyb28 with SMTP id 28so1413060wyb.19 for ; Thu, 03 Feb 2011 10:03:55 -0800 (PST) Received: by 10.227.141.67 with SMTP id l3mr11091822wbu.104.1296756235054; Thu, 03 Feb 2011 10:03:55 -0800 (PST) Received: from e200948.cambridge.arm.com (host86-160-160-30.range86-160.btcentralplus.com [86.160.160.30]) by mx.google.com with ESMTPS id x1sm307153wbh.14.2011.02.03.10.03.53 (version=SSLv3 cipher=RC4-MD5); Thu, 03 Feb 2011 10:03:54 -0800 (PST) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: Dave Martin , Tony Lindgren , Santosh Shilimkar , Jean Pihet , linux-omap@vger.kernel.org, Nicolas Pitre Subject: [PATCH v2 4/5] ARM: omap3: Thumb-2 compatibility for sram34xx.S Date: Thu, 3 Feb 2011 18:02:40 +0000 Message-Id: <1296756161-26092-5-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1296756161-26092-1-git-send-email-dave.martin@linaro.org> References: <1296756161-26092-1-git-send-email-dave.martin@linaro.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 03 Feb 2011 18:03:57 +0000 (UTC) diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 7f893a2..829d235 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -116,24 +116,34 @@ ENTRY(omap3_sram_configure_core_dpll) @ pull the extra args off the stack @ and store them in SRAM + +@ PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a +@ base instead. +@ Be careful not to clobber r7 when maintaing this file. + THUMB( adr r7, omap3_sram_configure_core_dpll ) + .macro strtext Rt:req, label:req + ARM( str \Rt, \label ) + THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] ) + .endm + ldr r4, [sp, #52] - str r4, omap_sdrc_rfr_ctrl_0_val + strtext r4, omap_sdrc_rfr_ctrl_0_val ldr r4, [sp, #56] - str r4, omap_sdrc_actim_ctrl_a_0_val + strtext r4, omap_sdrc_actim_ctrl_a_0_val ldr r4, [sp, #60] - str r4, omap_sdrc_actim_ctrl_b_0_val + strtext r4, omap_sdrc_actim_ctrl_b_0_val ldr r4, [sp, #64] - str r4, omap_sdrc_mr_0_val + strtext r4, omap_sdrc_mr_0_val ldr r4, [sp, #68] - str r4, omap_sdrc_rfr_ctrl_1_val + strtext r4, omap_sdrc_rfr_ctrl_1_val cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0, beq skip_cs1_params @ do not use cs1 params ldr r4, [sp, #72] - str r4, omap_sdrc_actim_ctrl_a_1_val + strtext r4, omap_sdrc_actim_ctrl_a_1_val ldr r4, [sp, #76] - str r4, omap_sdrc_actim_ctrl_b_1_val + strtext r4, omap_sdrc_actim_ctrl_b_1_val ldr r4, [sp, #80] - str r4, omap_sdrc_mr_1_val + strtext r4, omap_sdrc_mr_1_val skip_cs1_params: mrc p15, 0, r8, c1, c0, 0 @ read ctrl register bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction @@ -271,6 +281,7 @@ skip_cs1_prog: ldr r12, [r11] @ posted-write barrier for SDRC bx lr + .align omap3_sdrc_power: .word OMAP34XX_SDRC_REGADDR(SDRC_POWER) omap3_cm_clksel1_pll: @@ -319,6 +330,7 @@ omap3_sdrc_dlla_ctrl: .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) core_m2_mask_val: .word 0x07FFFFFF +ENDPROC(omap3_sram_configure_core_dpll) ENTRY(omap3_sram_configure_core_dpll_sz) .word . - omap3_sram_configure_core_dpll