@@ -170,6 +170,31 @@ static int omap4_enter_idle_bm(struct cpuidle_device *dev,
}
/**
+ * omap4_cpuidle_update_states() - Update the cpuidle states
+ * @mpu_deepest_state: Enable states upto and including this for mpu domain
+ * @core_deepest_state: Enable states upto and including this for core domain
+ *
+ * This goes through the list of states available and enables and disables the
+ * validity of C states based on deepest state that can be achieved for the
+ * variable domain
+ */
+void omap4_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
+{
+ int i;
+
+ for (i = OMAP4_STATE_C1; i < OMAP4_MAX_STATES; i++) {
+ struct omap4_processor_cx *cx = &omap4_power_states[i];
+
+ if ((cx->mpu_state >= mpu_deepest_state) &&
+ (cx->core_state >= core_deepest_state)) {
+ cx->valid = 1;
+ } else {
+ cx->valid = 0;
+ }
+ }
+}
+
+/**
* omap4_init_power_states - Initialises the OMAP4 specific C states.
*
*/
@@ -325,6 +350,11 @@ int __init omap4_idle_init(void)
}
}
+ if (enable_off_mode)
+ omap4_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
+ else
+ omap4_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
+
return 0;
}
#else
@@ -77,6 +77,7 @@ extern u32 sleep_while_idle;
#if defined(CONFIG_CPU_IDLE)
extern void omap3_cpuidle_update_states(u32, u32);
+extern void omap4_cpuidle_update_states(u32, u32);
#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
@@ -183,6 +183,10 @@ void omap4_pm_off_mode_enable(int enable)
else
state = PWRDM_POWER_RET;
+#ifdef CONFIG_CPU_IDLE
+ omap4_cpuidle_update_states(state, PWRDM_POWER_ON);
+#endif
+
list_for_each_entry(pwrst, &pwrst_list, node) {
/* FIXME: Remove this check when core retention is supported */
if (!strcmp(pwrst->pwrdm->name, "mpu_pwrdm")) {