From patchwork Thu Apr 14 21:52:48 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Guzman Lugo, Fernando" X-Patchwork-Id: 709761 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3ELrQdR000398 for ; Thu, 14 Apr 2011 21:53:26 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752703Ab1DNVxZ (ORCPT ); Thu, 14 Apr 2011 17:53:25 -0400 Received: from na3sys009aog114.obsmtp.com ([74.125.149.211]:49138 "EHLO na3sys009aog114.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751192Ab1DNVxX (ORCPT ); Thu, 14 Apr 2011 17:53:23 -0400 Received: from mail-yw0-f53.google.com ([209.85.213.53]) (using TLSv1) by na3sys009aob114.postini.com ([74.125.148.12]) with SMTP ID DSNKTads0lbHJ8Vpfq+ptHaITlzTfjW4eKR6@postini.com; Thu, 14 Apr 2011 14:53:23 PDT Received: by mail-yw0-f53.google.com with SMTP id 2so858899ywl.26 for ; Thu, 14 Apr 2011 14:53:22 -0700 (PDT) Received: by 10.151.131.15 with SMTP id i15mr1998783ybn.386.1302818001844; Thu, 14 Apr 2011 14:53:21 -0700 (PDT) Received: from localhost.localdomain (dragon.ti.com [192.94.94.33]) by mx.google.com with ESMTPS id w15sm2863505ybk.16.2011.04.14.14.53.20 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 14 Apr 2011 14:53:21 -0700 (PDT) From: Fernando Guzman Lugo To: , , Cc: , , Ramesh Gupta , Hari Kanigeri , Fernando Guzman Lugo Subject: [PATCH] OMAP: iommu flush page table entries from L1 and L2 cache Date: Thu, 14 Apr 2011 16:52:48 -0500 Message-Id: <1302817968-28516-1-git-send-email-fernando.lugo@ti.com> X-Mailer: git-send-email 1.7.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 14 Apr 2011 21:53:26 +0000 (UTC) From: Ramesh Gupta This patch is to flush the iommu page table entries from L1 and L2 caches using dma_map_single. This also simplifies the implementation by removing the functions flush_iopgd_range/flush_iopte_range. Change-Id: I19c0bf437d75c79084b2fa28c7da50a4c84b91a0 Signed-off-by: Ramesh Gupta Signed-off-by: Hari Kanigeri Signed-off-by: Fernando Guzman Lugo --- arch/arm/plat-omap/iommu.c | 41 ++++++++++------------------------------- 1 files changed, 10 insertions(+), 31 deletions(-) diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 8a51fd5..1fb5e41 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -18,6 +18,7 @@ #include #include #include +#include #include @@ -466,29 +467,6 @@ EXPORT_SYMBOL_GPL(foreach_iommu_device); #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ -/* - * H/W pagetable operations - */ -static void flush_iopgd_range(u32 *first, u32 *last) -{ - /* FIXME: L2 cache should be taken care of if it exists */ - do { - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" - : : "r" (first)); - first += L1_CACHE_BYTES / sizeof(*first); - } while (first <= last); -} - -static void flush_iopte_range(u32 *first, u32 *last) -{ - /* FIXME: L2 cache should be taken care of if it exists */ - do { - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" - : : "r" (first)); - first += L1_CACHE_BYTES / sizeof(*first); - } while (first <= last); -} - static void iopte_free(u32 *iopte) { /* Note: freed iopte's must be clean ready for re-use */ @@ -515,7 +493,7 @@ static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da) return ERR_PTR(-ENOMEM); *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; - flush_iopgd_range(iopgd, iopgd); + dma_map_single(obj->dev, iopgd, 1, DMA_TO_DEVICE); dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); } else { @@ -544,7 +522,7 @@ static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot) } *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; - flush_iopgd_range(iopgd, iopgd); + dma_map_single(obj->dev, iopgd, 1, DMA_TO_DEVICE); return 0; } @@ -561,7 +539,7 @@ static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot) for (i = 0; i < 16; i++) *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; - flush_iopgd_range(iopgd, iopgd + 15); + dma_map_single(obj->dev, iopgd, 16, DMA_TO_DEVICE); return 0; } @@ -574,7 +552,7 @@ static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot) return PTR_ERR(iopte); *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; - flush_iopte_range(iopte, iopte); + dma_map_single(obj->dev, iopte, 1, DMA_TO_DEVICE); dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", __func__, da, pa, iopte, *iopte); @@ -599,7 +577,7 @@ static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot) for (i = 0; i < 16; i++) *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; - flush_iopte_range(iopte, iopte + 15); + dma_map_single(obj->dev, iopte, 15, DMA_TO_DEVICE); return 0; } @@ -703,7 +681,8 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) } bytes *= nent; memset(iopte, 0, nent * sizeof(*iopte)); - flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); + dma_map_single(obj->dev, iopte, nent * sizeof(*iopte), + DMA_TO_DEVICE); /* * do table walk to check if this table is necessary or not @@ -725,7 +704,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) bytes *= nent; } memset(iopgd, 0, nent * sizeof(*iopgd)); - flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); + dma_map_single(obj->dev, iopgd, nent * sizeof(*iopgd), DMA_TO_DEVICE); out: return bytes; } @@ -770,7 +749,7 @@ static void iopgtable_clear_entry_all(struct iommu *obj) iopte_free(iopte_offset(iopgd, 0)); *iopgd = 0; - flush_iopgd_range(iopgd, iopgd); + dma_map_single(obj->dev, iopgd, 1, DMA_TO_DEVICE); } flush_iotlb_all(obj);