From patchwork Thu Apr 21 20:35:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 725641 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3LKXYGO017102 for ; Thu, 21 Apr 2011 20:33:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754367Ab1DUUdl (ORCPT ); Thu, 21 Apr 2011 16:33:41 -0400 Received: from na3sys009aog114.obsmtp.com ([74.125.149.211]:60309 "EHLO na3sys009aog114.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752955Ab1DUUdi (ORCPT ); Thu, 21 Apr 2011 16:33:38 -0400 Received: from mail-pz0-f47.google.com ([209.85.210.47]) (using TLSv1) by na3sys009aob114.postini.com ([74.125.148.12]) with SMTP ID DSNKTbCUob212o8cTKQzb88paeYVT/34etGN@postini.com; Thu, 21 Apr 2011 13:33:38 PDT Received: by mail-pz0-f47.google.com with SMTP id 35so50488pzk.6 for ; Thu, 21 Apr 2011 13:33:37 -0700 (PDT) Received: by 10.68.63.106 with SMTP id f10mr469340pbs.380.1303418017193; Thu, 21 Apr 2011 13:33:37 -0700 (PDT) Received: from localhost (c-24-18-179-55.hsd1.wa.comcast.net [24.18.179.55]) by mx.google.com with ESMTPS id t4sm1514007pbl.45.2011.04.21.13.33.36 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 21 Apr 2011 13:33:36 -0700 (PDT) From: Kevin Hilman To: linux-omap@vger.kernel.org Cc: charu@ti.com Subject: [PATCH 4/9] OMAP: GPIO: _get_gpio_irqbank_mask: replace hard-coded mask with bank->width Date: Thu, 21 Apr 2011 13:35:22 -0700 Message-Id: <1303418127-4310-5-git-send-email-khilman@ti.com> X-Mailer: git-send-email 1.7.4 In-Reply-To: <1303418127-4310-1-git-send-email-khilman@ti.com> References: <1303418127-4310-1-git-send-email-khilman@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 21 Apr 2011 20:33:54 +0000 (UTC) Replace hard-coded mask values with bank->width which is already coming from platform_data. Signed-off-by: Kevin Hilman --- arch/arm/plat-omap/gpio.c | 8 +------- 1 files changed, 1 insertions(+), 7 deletions(-) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index d1d3397..b66f374 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -823,46 +823,40 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) void __iomem *reg = bank->base; int inv = 0; u32 l; - u32 mask; + u32 mask = (1 << bank->width) - 1; switch (bank->method) { #ifdef CONFIG_ARCH_OMAP1 case METHOD_MPUIO: reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; - mask = 0xffff; inv = 1; break; #endif #ifdef CONFIG_ARCH_OMAP15XX case METHOD_GPIO_1510: reg += OMAP1510_GPIO_INT_MASK; - mask = 0xffff; inv = 1; break; #endif #ifdef CONFIG_ARCH_OMAP16XX case METHOD_GPIO_1610: reg += OMAP1610_GPIO_IRQENABLE1; - mask = 0xffff; break; #endif #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) case METHOD_GPIO_7XX: reg += OMAP7XX_GPIO_INT_MASK; - mask = 0xffffffff; inv = 1; break; #endif #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) case METHOD_GPIO_24XX: reg += OMAP24XX_GPIO_IRQENABLE1; - mask = 0xffffffff; break; #endif #if defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_44XX: reg += OMAP4_GPIO_IRQSTATUSSET0; - mask = 0xffffffff; break; #endif default: