From patchwork Mon May 9 14:45:52 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: R Sricharan X-Patchwork-Id: 769482 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p49EkKxi012831 for ; Mon, 9 May 2011 14:46:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753877Ab1EIOqR (ORCPT ); Mon, 9 May 2011 10:46:17 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:55823 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751881Ab1EIOqQ (ORCPT ); Mon, 9 May 2011 10:46:16 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p49EkC86027539 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 9 May 2011 09:46:14 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p49Ek7hA009461; Mon, 9 May 2011 20:16:07 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Mon, 9 May 2011 20:16:07 +0530 Received: from localhost.localdomain ([172.24.190.77]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p49Ek5rQ005537; Mon, 9 May 2011 20:16:06 +0530 (IST) From: sricharan To: CC: sricharan , Paul Wamsley , Santosh Shilimkar Subject: [PATCH] omap3: l3: Temporary fix to avoid the kernel hang with beagle board. Date: Mon, 9 May 2011 20:15:52 +0530 Message-ID: <1304952352-27837-1-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Mon, 09 May 2011 14:46:21 +0000 (UTC) Paul Walmsley reported a kernel hang issue with beagle board during boot. This is an intermittent bug and the execution was found to be stuck at the l3 interrupt handler. This was due to a dss initiator agent timeout occuring during the boot even when there is no actual interconnect access made by the dss. since the reason for the dss timeout is not root caused yet, the time out feature is disabled at the interconnect level. Note that this is a temporary fix that should be removed once the dss interconnect agent timeout issue is resolved. Thanks to Paul Walmsley for reporting and helping in reproducing this issue. Signed-off-by: sricharan Cc: Paul Wamsley Cc: Santosh Shilimkar --- arch/arm/mach-omap2/omap_l3_smx.c | 11 +++++++++++ arch/arm/mach-omap2/omap_l3_smx.h | 2 ++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c index 4321e79..4ea7dcd 100644 --- a/arch/arm/mach-omap2/omap_l3_smx.c +++ b/arch/arm/mach-omap2/omap_l3_smx.c @@ -248,6 +248,17 @@ static int __init omap3_l3_probe(struct platform_device *pdev) goto err2; } + /* + * FIX ME: dss interconnect timeout error. + * Disable the l3 timeout reporting feature for all modules. + * Also reset the dss initiator agent with which the error is seen + * to clear the interrupt. This is a temporary fix and should be + * removed after root causing the issue. + */ + omap3_l3_writell(l3->rt, L3_RT_NETWORK_CONTROL, 0x0); + omap3_l3_writell(l3->rt + L3_DSS_IA_CONTROL, L3_AGENT_CONTROL, 0x1); + omap3_l3_writell(l3->rt + L3_DSS_IA_CONTROL, L3_AGENT_CONTROL, 0x0); + l3->debug_irq = platform_get_irq(pdev, 0); ret = request_irq(l3->debug_irq, omap3_l3_app_irq, IRQF_DISABLED | IRQF_TRIGGER_RISING, diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h index ba2ed9a..96fff9d 100644 --- a/arch/arm/mach-omap2/omap_l3_smx.h +++ b/arch/arm/mach-omap2/omap_l3_smx.h @@ -35,6 +35,8 @@ #define L3_ERROR_LOG_SECONDARY (1 << 30) #define L3_ERROR_LOG_ADDR 0x060 +#define L3_RT_NETWORK_CONTROL 0x078 +#define L3_DSS_IA_CONTROL 0x5400 /* Register definitions for Sideband Interconnect */ #define L3_SI_CONTROL 0x020