From patchwork Sun May 15 21:45:57 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 786422 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p4FLkBu2017283 for ; Sun, 15 May 2011 21:46:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753233Ab1EOVqM (ORCPT ); Sun, 15 May 2011 17:46:12 -0400 Received: from mail-ew0-f46.google.com ([209.85.215.46]:44063 "EHLO mail-ew0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752715Ab1EOVqJ (ORCPT ); Sun, 15 May 2011 17:46:09 -0400 Received: by mail-ew0-f46.google.com with SMTP id 4so1103567ewy.19 for ; Sun, 15 May 2011 14:46:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:cc:subject:date:message-id :x-mailer:in-reply-to:references; bh=2AhGE7tZJ6bxoT0RRWTUy4byTBgonyi+8sFvmESMzqs=; b=iiPene2jYljNSV2fq6V0XfHuyg+YF4pZdJUm++E1WqrRnqTqLtW/b1aq1UWiWdIneh isag+Ayog6xmemy2V/7LCNO6T9OFnDyjh8rKM++QTb2+WNGWP8xZlyh8KtyINEXa8W6F M8clX6jZlAJnT5Ej6oDYG55O/oj8Yp5ovOOe4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=TpfNyDGwOcZOyL3MP4MjgC8ABd1X0uu38x8hNQCSArDWxxxG4wyZCIG7KVdMuRqHJk BTEQy6zZbMUubtR5Gv+gHwhA3cYYfpyEMbGXxvDcztNOnZEqj36jQ6gCiCzLUPuuw07O z65NunLeHXtNQb6LQkBdVHeHMlbtFEmbxeAIE= Received: by 10.213.9.138 with SMTP id l10mr560257ebl.5.1305495968508; Sun, 15 May 2011 14:46:08 -0700 (PDT) Received: from localhost.localdomain (a88-114-218-111.elisa-laajakaista.fi [88.114.218.111]) by mx.google.com with ESMTPS id r12sm2984324eeb.18.2011.05.15.14.46.06 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 May 2011 14:46:07 -0700 (PDT) From: Vladimir Zapolskiy To: Tony Lindgren , Benoit Cousson Cc: , , Vladimir Zapolskiy Subject: [PATCHv2 1/2] [RFC] OMAP4: clock data: shrink clock data utilizing preprocessor. Date: Mon, 16 May 2011 00:45:57 +0300 Message-Id: <1305495958-2236-2-git-send-email-vzapolskiy@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1305495958-2236-1-git-send-email-vzapolskiy@gmail.com> References: <1305495958-2236-1-git-send-email-vzapolskiy@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Sun, 15 May 2011 21:46:13 +0000 (UTC) This mass change reduces homogeneous data chunks along clock definitions. No semantical difference is added in the change. Signed-off-by: Vladimir Zapolskiy --- arch/arm/mach-omap2/clock44xx_data.c | 1638 ++++++++++------------------------ 1 files changed, 470 insertions(+), 1168 deletions(-) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 8c96567..423f180 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -7,6 +7,7 @@ * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) * Benoit Cousson (b-cousson@ti.com) + * Vladimir Zapolskiy (vzapolskiy@gmail.com) * * This file is automatically generated from the OMAP hardware databases. * We respectfully ask that any modifications to this file be coordinated @@ -42,129 +43,218 @@ #define OMAP4430_MODULEMODE_HWCTRL 0 #define OMAP4430_MODULEMODE_SWCTRL 1 -/* Root clocks */ - -static struct clk extalt_clkin_ck = { - .name = "extalt_clkin_ck", - .rate = 59000000, - .ops = &clkops_null, -}; - -static struct clk pad_clks_ck = { - .name = "pad_clks_ck", - .rate = 12000000, - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CLKSEL_ABE, - .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, -}; - -static struct clk pad_slimbus_core_clks_ck = { - .name = "pad_slimbus_core_clks_ck", - .rate = 12000000, - .ops = &clkops_null, -}; - -static struct clk secure_32k_clk_src_ck = { - .name = "secure_32k_clk_src_ck", - .rate = 32768, - .ops = &clkops_null, -}; - -static struct clk slimbus_clk = { - .name = "slimbus_clk", - .rate = 12000000, - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CLKSEL_ABE, - .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, -}; - -static struct clk sys_32k_ck = { - .name = "sys_32k_ck", - .rate = 32768, - .ops = &clkops_null, -}; - -static struct clk virt_12000000_ck = { - .name = "virt_12000000_ck", - .ops = &clkops_null, - .rate = 12000000, -}; - -static struct clk virt_13000000_ck = { - .name = "virt_13000000_ck", - .ops = &clkops_null, - .rate = 13000000, -}; - -static struct clk virt_16800000_ck = { - .name = "virt_16800000_ck", - .ops = &clkops_null, - .rate = 16800000, -}; - -static struct clk virt_19200000_ck = { - .name = "virt_19200000_ck", - .ops = &clkops_null, - .rate = 19200000, -}; - -static struct clk virt_26000000_ck = { - .name = "virt_26000000_ck", - .ops = &clkops_null, - .rate = 26000000, -}; +#define CLOCK_FLAGS_ENABLE(...) \ + .flags = ENABLE_ON_INIT, \ + ##__VA_ARGS__ + +#define CLOCK_OPS(_ops, ...) \ + .ops = &_ops, \ + ##__VA_ARGS__ + +#define CLOCK_OPS_NULL(...) \ + CLOCK_OPS(clkops_null, ##__VA_ARGS__) + +#define CLOCK_OPS_DPLL(...) \ + CLOCK_OPS(clkops_omap4_dpllmx_ops, ##__VA_ARGS__) + +#define CLOCK_OPS_DFLT0(_reg, _bit, ...) \ + .ops = &clkops_omap2_dflt, \ + .enable_reg = OMAP4430_##_reg, \ + .enable_bit = OMAP4430_##_bit##_SHIFT, \ + ##__VA_ARGS__ + +#define CLOCK_OPS_DFLT(_reg, _bit, ...) \ + .ops = &clkops_omap2_dflt, \ + .enable_reg = OMAP4430_##_reg##_CLKCTRL, \ + .enable_bit = OMAP4430_##_bit##_SHIFT, \ + ##__VA_ARGS__ + +#define CLOCK_OPS_DFLT_SW(_reg, ...) \ + .ops = &clkops_omap2_dflt, \ + .enable_reg = OMAP4430_##_reg##_CLKCTRL, \ + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, \ + ##__VA_ARGS__ + +#define CLOCK_OPS_DFLT_HW(_reg, ...) \ + .ops = &clkops_omap2_dflt, \ + .enable_reg = OMAP4430_##_reg##_CLKCTRL, \ + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, \ + ##__VA_ARGS__ + +#define CLOCK_OPS_DFLT2(_reg, ...) \ + .ops = &clkops_omap2_dflt, \ + .enable_reg = OMAP4_##_reg, \ + .enable_bit = OMAP4_ENABLE_SHIFT, \ + ##__VA_ARGS__ + +#define CLOCK_RECALC(_recalc, ...) \ + .recalc = &_recalc, \ + ##__VA_ARGS__ + +#define CLOCK_RECALC_FOLLOWPARENT(...) \ + CLOCK_RECALC(followparent_recalc, ##__VA_ARGS__) + +#define CLOCK_RECALC_CLKSEL(...) \ + CLOCK_RECALC(omap2_clksel_recalc, ##__VA_ARGS__) + +#define CLOCK_RECALC_CLKOUTX2(...) \ + .flags = CLOCK_CLKOUTX2, \ + CLOCK_RECALC(omap3_clkoutx2_recalc, ##__VA_ARGS__) + +#define CLOCK_RECALC_RATE(_recalc, _round_rate, _set_rate, ...) \ + .recalc = &_recalc, \ + .round_rate = &_round_rate, \ + .set_rate = &_set_rate, \ + ##__VA_ARGS__ + +#define CLOCK_RECALC_FIXED(_div, ...) \ + .recalc = &omap_fixed_divisor_recalc, \ + .fixed_div = _div, \ + CLOCK_OPS_NULL(), \ + ##__VA_ARGS__ + +#define CLOCK_RECALC_RATE_CLKSEL(...) \ + CLOCK_RECALC_RATE(omap2_clksel_recalc, \ + omap2_clksel_round_rate, \ + omap2_clksel_set_rate, ##__VA_ARGS__) + +#define CLOCK_RECALC_RATE_DPLL(_dpll_data, ...) \ + .init = &omap2_init_dpll_parent, \ + .dpll_data = &_dpll_data, \ + CLOCK_RECALC_RATE(omap3_dpll_recalc, \ + omap2_dpll_round_rate, \ + omap3_noncore_dpll_set_rate), \ + CLOCK_OPS(clkops_omap3_noncore_dpll_ops), \ + ##__VA_ARGS__ + +#define CLOCK_CLKSEL_DPLL(_reg, ...) \ + .clksel_reg = OMAP4430_##_reg, \ + CLOCK_OPS_DPLL(), \ + ##__VA_ARGS__ + +#define CLOCK_CLKSEL_INIT(_sel, _reg, _mask, ...) \ + .init = &omap2_init_clksel_parent, \ + .clksel = _sel, \ + .clksel_reg = OMAP4430_##_reg, \ + .clksel_mask = OMAP4430_##_mask##_MASK, \ + CLOCK_OPS_NULL(), \ + CLOCK_RECALC_CLKSEL(), \ + ##__VA_ARGS__ + +#define CLOCK_CLKSEL_INIT_SW(_sel, _reg, _mask, ...) \ + .init = &omap2_init_clksel_parent, \ + .clksel = _sel, \ + .clksel_reg = OMAP4430_##_reg##_CLKCTRL, \ + .clksel_mask = OMAP4430_##_mask##_MASK, \ + CLOCK_OPS_DFLT_SW(_reg), \ + CLOCK_RECALC_CLKSEL(), \ + ##__VA_ARGS__ + +#define CLOCK_CLKSEL_INIT2(_sel, _reg, _mask, ...) \ + .init = &omap2_init_clksel_parent, \ + .clksel = _sel, \ + .clksel_reg = OMAP4_##_reg, \ + .clksel_mask = OMAP4_##_mask##_MASK, \ + CLOCK_RECALC_CLKSEL(), \ + ##__VA_ARGS__ + +#define CLOCK_CLKSEL0(_sel, _reg, _mask, ...) \ + .clksel = _sel, \ + .clksel_reg = OMAP4430_##_reg, \ + .clksel_mask = OMAP4430_##_mask##_MASK, \ + CLOCK_RECALC_CLKSEL(), \ + ##__VA_ARGS__ + +#define CLOCK_CLKSEL(_sel, _reg, _mask, ...) \ + .clksel = _sel, \ + .clksel_reg = OMAP4430_##_reg, \ + .clksel_mask = OMAP4430_##_mask##_MASK, \ + CLOCK_RECALC_RATE_CLKSEL(), \ + ##__VA_ARGS__ + +#define DEFINE_ROOT_CLOCK(_name, _rate, ...) \ + static struct clk _name = { \ + .name = #_name, \ + .rate = _rate, \ + ##__VA_ARGS__ \ + } -static struct clk virt_27000000_ck = { - .name = "virt_27000000_ck", - .ops = &clkops_null, - .rate = 27000000, -}; +#define DEFINE_CLOCK(_name, _parent, ...) \ + static struct clk _name = { \ + .name = #_name, \ + .parent = &_parent, \ + ##__VA_ARGS__ \ + } -static struct clk virt_38400000_ck = { - .name = "virt_38400000_ck", - .ops = &clkops_null, - .rate = 38400000, -}; +#define DEFINE_CLOCK_DM(_name, _parent, _clkdm, ...) \ + DEFINE_CLOCK(_name, _parent, \ + .clkdm_name = #_clkdm, ##__VA_ARGS__) -static const struct clksel_rate div_1_0_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +#define DEFINE_CLKSEL(_name, _parent, _rates) \ + static const struct clksel _name[] = { \ + { .parent = &_parent, .rates = _rates }, \ + { .parent = NULL }, \ + } -static const struct clksel_rate div_1_1_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +#define DEFINE_CLKSEL2(_name, _parent0, _parent1) \ + static const struct clksel _name[] = { \ + { .parent = &_parent0, .rates = div_1_0_rates }, \ + { .parent = &_parent1, .rates = div_1_1_rates }, \ + { .parent = NULL }, \ + } -static const struct clksel_rate div_1_2_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +#define DEFINE_CLKSEL3(_name, _parent0, _parent1, _parent2) \ + static const struct clksel _name[] = { \ + { .parent = &_parent0, .rates = div_1_0_rates }, \ + { .parent = &_parent1, .rates = div_1_1_rates }, \ + { .parent = &_parent2, .rates = div_1_2_rates }, \ + { .parent = NULL }, \ + } -static const struct clksel_rate div_1_3_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +#define DEFINE_CLKSEL_RATE(n) \ + static const struct clksel_rate div_1_##n##_rates[] = { \ + { .div = 1, .val = n, .flags = RATE_IN_4430 }, \ + { .div = 0 }, \ + } -static const struct clksel_rate div_1_4_rates[] = { - { .div = 1, .val = 4, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +#define DEFINE_CLKSEL_RATE2(_range, _div0, _div1) \ + static const struct clksel_rate div2_##_range##_rates[] = { \ + { .div = _div0, .val = 0, .flags = RATE_IN_4430 }, \ + { .div = _div1, .val = 1, .flags = RATE_IN_4430 }, \ + { .div = 0 }, \ + } -static const struct clksel_rate div_1_5_rates[] = { - { .div = 1, .val = 5, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +/* +#define DEFINE_DPLL_DATA(_name, ) +*/ -static const struct clksel_rate div_1_6_rates[] = { - { .div = 1, .val = 6, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +/* Root clocks */ -static const struct clksel_rate div_1_7_rates[] = { - { .div = 1, .val = 7, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +DEFINE_ROOT_CLOCK(extalt_clkin_ck, 59000000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(pad_slimbus_core_clks_ck, 12000000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(secure_32k_clk_src_ck, 32768, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(sys_32k_ck, 32768, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(virt_12000000_ck, 12000000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(virt_13000000_ck, 13000000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(virt_16800000_ck, 16800000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(virt_19200000_ck, 19200000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(virt_26000000_ck, 26000000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(virt_27000000_ck, 27000000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(virt_38400000_ck, 38400000, CLOCK_OPS_NULL()); + +DEFINE_ROOT_CLOCK(pad_clks_ck, 12000000, + CLOCK_OPS_DFLT0(CM_CLKSEL_ABE, PAD_CLKS_GATE)); +DEFINE_ROOT_CLOCK(slimbus_clk, 12000000, + CLOCK_OPS_DFLT0(CM_CLKSEL_ABE, SLIMBUS_CLK_GATE)); + +DEFINE_CLKSEL_RATE(0); +DEFINE_CLKSEL_RATE(1); +DEFINE_CLKSEL_RATE(2); +DEFINE_CLKSEL_RATE(3); +DEFINE_CLKSEL_RATE(4); +DEFINE_CLKSEL_RATE(5); +DEFINE_CLKSEL_RATE(6); +DEFINE_CLKSEL_RATE(7); static const struct clksel sys_clkin_sel[] = { { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, @@ -177,72 +267,24 @@ static const struct clksel sys_clkin_sel[] = { { .parent = NULL }, }; -static struct clk sys_clkin_ck = { - .name = "sys_clkin_ck", - .rate = 38400000, - .clksel = sys_clkin_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_SYS_CLKSEL, - .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk tie_low_clock_ck = { - .name = "tie_low_clock_ck", - .rate = 0, - .ops = &clkops_null, -}; - -static struct clk utmi_phy_clkout_ck = { - .name = "utmi_phy_clkout_ck", - .rate = 60000000, - .ops = &clkops_null, -}; - -static struct clk xclk60mhsp1_ck = { - .name = "xclk60mhsp1_ck", - .rate = 60000000, - .ops = &clkops_null, -}; - -static struct clk xclk60mhsp2_ck = { - .name = "xclk60mhsp2_ck", - .rate = 60000000, - .ops = &clkops_null, -}; +DEFINE_ROOT_CLOCK(sys_clkin_ck, 38400000, + CLOCK_CLKSEL_INIT(sys_clkin_sel, CM_SYS_CLKSEL, SYS_CLKSEL)); -static struct clk xclk60motg_ck = { - .name = "xclk60motg_ck", - .rate = 60000000, - .ops = &clkops_null, -}; +DEFINE_ROOT_CLOCK(tie_low_clock_ck, 0, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(utmi_phy_clkout_ck, 60000000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(xclk60mhsp1_ck, 60000000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(xclk60mhsp2_ck, 60000000, CLOCK_OPS_NULL()); +DEFINE_ROOT_CLOCK(xclk60motg_ck, 60000000, CLOCK_OPS_NULL()); /* Module clocks and DPLL outputs */ -static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk abe_dpll_bypass_clk_mux_ck = { - .name = "abe_dpll_bypass_clk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; +DEFINE_CLKSEL2(abe_dpll_bypass_clk_mux_sel, sys_clkin_ck, sys_32k_ck); -static struct clk abe_dpll_refclk_mux_ck = { - .name = "abe_dpll_refclk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; +DEFINE_CLOCK(abe_dpll_bypass_clk_mux_ck, sys_clkin_ck, + CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT()); +DEFINE_CLOCK(abe_dpll_refclk_mux_ck, sys_clkin_ck, + CLOCK_CLKSEL_INIT(abe_dpll_bypass_clk_mux_sel, + CM_ABE_PLL_REF_CLKSEL, CLKSEL_0_0)); /* DPLL_ABE */ static struct dpll_data dpll_abe_dd = { @@ -263,26 +305,11 @@ static struct dpll_data dpll_abe_dd = { .min_divider = 1, }; +DEFINE_CLOCK(dpll_abe_ck, abe_dpll_refclk_mux_ck, + CLOCK_RECALC_RATE_DPLL(dpll_abe_dd)); -static struct clk dpll_abe_ck = { - .name = "dpll_abe_ck", - .parent = &abe_dpll_refclk_mux_ck, - .dpll_data = &dpll_abe_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static struct clk dpll_abe_x2_ck = { - .name = "dpll_abe_x2_ck", - .parent = &dpll_abe_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap3_clkoutx2_recalc, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, -}; +DEFINE_CLOCK(dpll_abe_x2_ck, dpll_abe_ck, + CLOCK_CLKSEL_DPLL(CM_DIV_M2_DPLL_ABE), CLOCK_RECALC_CLKOUTX2()); static const struct clksel_rate div31_1to31_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_4430 }, @@ -319,30 +346,13 @@ static const struct clksel_rate div31_1to31_rates[] = { { .div = 0 }, }; -static const struct clksel dpll_abe_m2x2_div[] = { - { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(dpll_abe_m2x2_div, dpll_abe_x2_ck, div31_1to31_rates); -static struct clk dpll_abe_m2x2_ck = { - .name = "dpll_abe_m2x2_ck", - .parent = &dpll_abe_x2_ck, - .clksel = dpll_abe_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_abe_m2x2_ck, dpll_abe_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_abe_m2x2_div, + CM_DIV_M2_DPLL_ABE, DPLL_CLKOUT_DIV)); -static struct clk abe_24m_fclk = { - .name = "abe_24m_fclk", - .parent = &dpll_abe_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 8, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLOCK(abe_24m_fclk, dpll_abe_m2x2_ck, CLOCK_RECALC_FIXED(8)); static const struct clksel_rate div3_1to4_rates[] = { { .div = 1, .val = 0, .flags = RATE_IN_4430 }, @@ -351,74 +361,28 @@ static const struct clksel_rate div3_1to4_rates[] = { { .div = 0 }, }; -static const struct clksel abe_clk_div[] = { - { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(abe_clk_div, dpll_abe_m2x2_ck, div3_1to4_rates); -static struct clk abe_clk = { - .name = "abe_clk", - .parent = &dpll_abe_m2x2_ck, - .clksel = abe_clk_div, - .clksel_reg = OMAP4430_CM_CLKSEL_ABE, - .clksel_mask = OMAP4430_CLKSEL_OPP_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(abe_clk, dpll_abe_m2x2_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(abe_clk_div, CM_CLKSEL_ABE, CLKSEL_OPP)); -static const struct clksel_rate div2_1to2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +DEFINE_CLKSEL_RATE2(1to2, 1, 2); -static const struct clksel aess_fclk_div[] = { - { .parent = &abe_clk, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(aess_fclk_div, abe_clk, div2_1to2_rates); -static struct clk aess_fclk = { - .name = "aess_fclk", - .parent = &abe_clk, - .clksel = aess_fclk_div, - .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(aess_fclk, abe_clk, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(aess_fclk_div, + CM1_ABE_AESS_CLKCTRL, CLKSEL_AESS_FCLK)); -static struct clk dpll_abe_m3x2_ck = { - .name = "dpll_abe_m3x2_ck", - .parent = &dpll_abe_x2_ck, - .clksel = dpll_abe_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, - .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_abe_m3x2_ck, dpll_abe_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_abe_m2x2_div, + CM_DIV_M3_DPLL_ABE, DPLL_CLKOUTHIF_DIV)); -static const struct clksel core_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL2(core_hsd_byp_clk_mux_sel, sys_clkin_ck, dpll_abe_m3x2_ck); -static struct clk core_hsd_byp_clk_mux_ck = { - .name = "core_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = core_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, - .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; +DEFINE_CLOCK(core_hsd_byp_clk_mux_ck, sys_clkin_ck, + CLOCK_CLKSEL_INIT(core_hsd_byp_clk_mux_sel, + CM_CLKSEL_DPLL_CORE, DPLL_BYP_CLKSEL)); /* DPLL_CORE */ static struct dpll_data dpll_core_dd = { @@ -439,107 +403,39 @@ static struct dpll_data dpll_core_dd = { .min_divider = 1, }; +/* originally round_rate/set_rate were NOT defined for dpll_core_ck */ +DEFINE_CLOCK(dpll_core_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_core_dd)); -static struct clk dpll_core_ck = { - .name = "dpll_core_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_core_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_core_dpll_ops, - .recalc = &omap3_dpll_recalc, -}; - -static struct clk dpll_core_x2_ck = { - .name = "dpll_core_x2_ck", - .parent = &dpll_core_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, -}; +DEFINE_CLOCK(dpll_core_x2_ck, dpll_core_ck, + CLOCK_OPS_NULL(), CLOCK_RECALC_CLKOUTX2()); -static const struct clksel dpll_core_m6x2_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(dpll_core_m6x2_div, dpll_core_x2_ck, div31_1to31_rates); -static struct clk dpll_core_m6x2_ck = { - .name = "dpll_core_m6x2_ck", - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_core_m6x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_core_m6x2_div, + CM_DIV_M6_DPLL_CORE, HSDIVIDER_CLKOUT3_DIV)); -static const struct clksel dbgclk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL2(dbgclk_mux_sel, sys_clkin_ck, dpll_core_m6x2_ck); -static struct clk dbgclk_mux_ck = { - .name = "dbgclk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK(dbgclk_mux_ck, sys_clkin_ck, + CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT()); -static const struct clksel dpll_core_m2_div[] = { - { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(dpll_core_m2_div, dpll_core_ck, div31_1to31_rates); -static struct clk dpll_core_m2_ck = { - .name = "dpll_core_m2_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_core_m2_ck, dpll_core_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_core_m2_div, + CM_DIV_M2_DPLL_CORE, DPLL_CLKOUT_DIV)); -static struct clk ddrphy_ck = { - .name = "ddrphy_ck", - .parent = &dpll_core_m2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLOCK(ddrphy_ck, dpll_core_m2_ck, CLOCK_RECALC_FIXED(2)); -static struct clk dpll_core_m5x2_ck = { - .name = "dpll_core_m5x2_ck", - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_core_m5x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_core_m6x2_div, + CM_DIV_M5_DPLL_CORE, HSDIVIDER_CLKOUT2_DIV)); -static const struct clksel div_core_div[] = { - { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(div_core_div, dpll_core_m5x2_ck, div2_1to2_rates); -static struct clk div_core_ck = { - .name = "div_core_ck", - .parent = &dpll_core_m5x2_ck, - .clksel = div_core_div, - .clksel_reg = OMAP4430_CM_CLKSEL_CORE, - .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(div_core_ck, dpll_core_m5x2_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(div_core_div, CM_CLKSEL_CORE, CLKSEL_CORE)); static const struct clksel_rate div4_1to8_rates[] = { { .div = 1, .val = 0, .flags = RATE_IN_4430 }, @@ -549,114 +445,40 @@ static const struct clksel_rate div4_1to8_rates[] = { { .div = 0 }, }; -static const struct clksel div_iva_hs_clk_div[] = { - { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(div_iva_hs_clk_div, dpll_core_m5x2_ck, div4_1to8_rates); -static struct clk div_iva_hs_clk = { - .name = "div_iva_hs_clk", - .parent = &dpll_core_m5x2_ck, - .clksel = div_iva_hs_clk_div, - .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, - .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(div_iva_hs_clk, dpll_core_m5x2_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(div_iva_hs_clk_div, CM_BYPCLK_DPLL_IVA, CLKSEL_0_1)); -static struct clk div_mpu_hs_clk = { - .name = "div_mpu_hs_clk", - .parent = &dpll_core_m5x2_ck, - .clksel = div_iva_hs_clk_div, - .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, - .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(div_mpu_hs_clk, dpll_core_m5x2_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(div_iva_hs_clk_div, CM_BYPCLK_DPLL_MPU, CLKSEL_0_1)); -static struct clk dpll_core_m4x2_ck = { - .name = "dpll_core_m4x2_ck", - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_core_m4x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_core_m6x2_div, + CM_DIV_M4_DPLL_CORE, HSDIVIDER_CLKOUT1_DIV)); -static struct clk dll_clk_div_ck = { - .name = "dll_clk_div_ck", - .parent = &dpll_core_m4x2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLOCK(dll_clk_div_ck, dpll_core_m4x2_ck, CLOCK_RECALC_FIXED(2)); -static const struct clksel dpll_abe_m2_div[] = { - { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(dpll_abe_m2_div, dpll_abe_ck, div31_1to31_rates); -static struct clk dpll_abe_m2_ck = { - .name = "dpll_abe_m2_ck", - .parent = &dpll_abe_ck, - .clksel = dpll_abe_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_abe_m2_ck, dpll_abe_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_abe_m2_div, + CM_DIV_M2_DPLL_ABE, DPLL_CLKOUT_DIV)); -static struct clk dpll_core_m3x2_ck = { - .name = "dpll_core_m3x2_ck", - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, - .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, - .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_core_m3x2_ck, dpll_core_x2_ck, + CLOCK_OPS_DFLT0(CM_DIV_M3_DPLL_CORE, DPLL_CLKOUTHIF_GATE_CTRL), + CLOCK_CLKSEL(dpll_core_m6x2_div, + CM_DIV_M3_DPLL_CORE, DPLL_CLKOUTHIF_DIV)); -static struct clk dpll_core_m7x2_ck = { - .name = "dpll_core_m7x2_ck", - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_core_m7x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_core_m6x2_div, + CM_DIV_M7_DPLL_CORE, HSDIVIDER_CLKOUT4_DIV)); -static const struct clksel iva_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL2(iva_hsd_byp_clk_mux_sel, sys_clkin_ck, div_iva_hs_clk); -static struct clk iva_hsd_byp_clk_mux_ck = { - .name = "iva_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = iva_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, - .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; +DEFINE_CLOCK(iva_hsd_byp_clk_mux_ck, sys_clkin_ck, + CLOCK_CLKSEL_INIT(iva_hsd_byp_clk_mux_sel, + CM_CLKSEL_DPLL_IVA, DPLL_BYP_CLKSEL)); /* DPLL_IVA */ static struct dpll_data dpll_iva_dd = { @@ -677,54 +499,21 @@ static struct dpll_data dpll_iva_dd = { .min_divider = 1, }; +DEFINE_CLOCK(dpll_iva_ck, sys_clkin_ck, + CLOCK_RECALC_RATE_DPLL(dpll_iva_dd)); -static struct clk dpll_iva_ck = { - .name = "dpll_iva_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_iva_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static struct clk dpll_iva_x2_ck = { - .name = "dpll_iva_x2_ck", - .parent = &dpll_iva_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, -}; +DEFINE_CLOCK(dpll_iva_x2_ck, dpll_iva_ck, + CLOCK_OPS_NULL(), CLOCK_RECALC_CLKOUTX2()); -static const struct clksel dpll_iva_m4x2_div[] = { - { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(dpll_iva_m4x2_div, dpll_iva_x2_ck, div31_1to31_rates); -static struct clk dpll_iva_m4x2_ck = { - .name = "dpll_iva_m4x2_ck", - .parent = &dpll_iva_x2_ck, - .clksel = dpll_iva_m4x2_div, - .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_iva_m4x2_ck, dpll_iva_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_iva_m4x2_div, + CM_DIV_M4_DPLL_IVA, HSDIVIDER_CLKOUT1_DIV)); -static struct clk dpll_iva_m5x2_ck = { - .name = "dpll_iva_m5x2_ck", - .parent = &dpll_iva_x2_ck, - .clksel = dpll_iva_m4x2_div, - .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_iva_m5x2_ck, dpll_iva_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_iva_m4x2_div, + CM_DIV_M5_DPLL_IVA, HSDIVIDER_CLKOUT2_DIV)); /* DPLL_MPU */ static struct dpll_data dpll_mpu_dd = { @@ -745,59 +534,21 @@ static struct dpll_data dpll_mpu_dd = { .min_divider = 1, }; +DEFINE_CLOCK(dpll_mpu_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_mpu_dd)); -static struct clk dpll_mpu_ck = { - .name = "dpll_mpu_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_mpu_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static const struct clksel dpll_mpu_m2_div[] = { - { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(dpll_mpu_m2_div, dpll_mpu_ck, div31_1to31_rates); -static struct clk dpll_mpu_m2_ck = { - .name = "dpll_mpu_m2_ck", - .parent = &dpll_mpu_ck, - .clksel = dpll_mpu_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_mpu_m2_ck, dpll_mpu_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_mpu_m2_div, + CM_DIV_M2_DPLL_MPU, DPLL_CLKOUT_DIV)); -static struct clk per_hs_clk_div_ck = { - .name = "per_hs_clk_div_ck", - .parent = &dpll_abe_m3x2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLOCK(per_hs_clk_div_ck, dpll_abe_m3x2_ck, CLOCK_RECALC_FIXED(2)); -static const struct clksel per_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL2(per_hsd_byp_clk_mux_sel, sys_clkin_ck, per_hs_clk_div_ck); -static struct clk per_hsd_byp_clk_mux_ck = { - .name = "per_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = per_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; +DEFINE_CLOCK(per_hsd_byp_clk_mux_ck, sys_clkin_ck, + CLOCK_CLKSEL_INIT(per_hsd_byp_clk_mux_sel, + CM_CLKSEL_DPLL_PER, DPLL_BYP_CLKSEL)); /* DPLL_PER */ static struct dpll_data dpll_per_dd = { @@ -818,122 +569,43 @@ static struct dpll_data dpll_per_dd = { .min_divider = 1, }; +DEFINE_CLOCK(dpll_per_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_per_dd)); -static struct clk dpll_per_ck = { - .name = "dpll_per_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_per_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; +DEFINE_CLKSEL(dpll_per_m2_div, dpll_per_ck, div31_1to31_rates); -static const struct clksel dpll_per_m2_div[] = { - { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; +DEFINE_CLOCK(dpll_per_m2_ck, dpll_per_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_per_m2_div, + CM_DIV_M2_DPLL_PER, DPLL_CLKOUT_DIV)); -static struct clk dpll_per_m2_ck = { - .name = "dpll_per_m2_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_per_x2_ck, dpll_per_ck, + CLOCK_CLKSEL_DPLL(CM_DIV_M2_DPLL_PER), CLOCK_RECALC_CLKOUTX2()); -static struct clk dpll_per_x2_ck = { - .name = "dpll_per_x2_ck", - .parent = &dpll_per_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap3_clkoutx2_recalc, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, -}; +DEFINE_CLKSEL(dpll_per_m2x2_div, dpll_per_x2_ck, div31_1to31_rates); -static const struct clksel dpll_per_m2x2_div[] = { - { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; +DEFINE_CLOCK(dpll_per_m2x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_per_m2x2_div, + CM_DIV_M2_DPLL_PER, DPLL_CLKOUT_DIV)); -static struct clk dpll_per_m2x2_ck = { - .name = "dpll_per_m2x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_per_m3x2_ck, dpll_per_x2_ck, + CLOCK_OPS_DFLT0(CM_DIV_M3_DPLL_PER, DPLL_CLKOUTHIF_GATE_CTRL), + CLOCK_CLKSEL(dpll_per_m2x2_div, + CM_DIV_M3_DPLL_PER, DPLL_CLKOUTHIF_DIV)); -static struct clk dpll_per_m3x2_ck = { - .name = "dpll_per_m3x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, - .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m4x2_ck = { - .name = "dpll_per_m4x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_per_m4x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_per_m2x2_div, + CM_DIV_M4_DPLL_PER, HSDIVIDER_CLKOUT1_DIV)); -static struct clk dpll_per_m5x2_ck = { - .name = "dpll_per_m5x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_per_m5x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_per_m2x2_div, + CM_DIV_M5_DPLL_PER, HSDIVIDER_CLKOUT2_DIV)); -static struct clk dpll_per_m6x2_ck = { - .name = "dpll_per_m6x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_per_m6x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_per_m2x2_div, + CM_DIV_M6_DPLL_PER, HSDIVIDER_CLKOUT3_DIV)); -static struct clk dpll_per_m7x2_ck = { - .name = "dpll_per_m7x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_per_m7x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_per_m2x2_div, + CM_DIV_M7_DPLL_PER, HSDIVIDER_CLKOUT4_DIV)); /* DPLL_UNIPRO */ static struct dpll_data dpll_unipro_dd = { @@ -955,50 +627,19 @@ static struct dpll_data dpll_unipro_dd = { .min_divider = 1, }; +DEFINE_CLOCK(dpll_unipro_ck, sys_clkin_ck, + CLOCK_RECALC_RATE_DPLL(dpll_unipro_dd)); -static struct clk dpll_unipro_ck = { - .name = "dpll_unipro_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_unipro_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static struct clk dpll_unipro_x2_ck = { - .name = "dpll_unipro_x2_ck", - .parent = &dpll_unipro_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, -}; +DEFINE_CLOCK(dpll_unipro_x2_ck, dpll_unipro_ck, + CLOCK_OPS_NULL(), CLOCK_RECALC_CLKOUTX2()); -static const struct clksel dpll_unipro_m2x2_div[] = { - { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(dpll_unipro_m2x2_div, dpll_unipro_x2_ck, div31_1to31_rates); -static struct clk dpll_unipro_m2x2_ck = { - .name = "dpll_unipro_m2x2_ck", - .parent = &dpll_unipro_x2_ck, - .clksel = dpll_unipro_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(dpll_unipro_m2x2_ck, dpll_unipro_x2_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_unipro_m2x2_div, + CM_DIV_M2_DPLL_UNIPRO, DPLL_CLKOUT_DIV)); -static struct clk usb_hs_clk_div_ck = { - .name = "usb_hs_clk_div_ck", - .parent = &dpll_abe_m3x2_ck, - .ops = &clkops_null, - .fixed_div = 3, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLOCK(usb_hs_clk_div_ck, dpll_abe_m3x2_ck, CLOCK_RECALC_FIXED(3)); /* DPLL_USB */ static struct dpll_data dpll_usb_dd = { @@ -1020,528 +661,189 @@ static struct dpll_data dpll_usb_dd = { .min_divider = 1, }; +DEFINE_CLOCK(dpll_usb_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_usb_dd)); -static struct clk dpll_usb_ck = { - .name = "dpll_usb_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_usb_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; +DEFINE_CLOCK(dpll_usb_clkdcoldo_ck, dpll_usb_ck, + CLOCK_CLKSEL_DPLL(CM_CLKDCOLDO_DPLL_USB), + CLOCK_RECALC_FOLLOWPARENT()); -static struct clk dpll_usb_clkdcoldo_ck = { - .name = "dpll_usb_clkdcoldo_ck", - .parent = &dpll_usb_ck, - .ops = &clkops_omap4_dpllmx_ops, - .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, - .recalc = &followparent_recalc, -}; +DEFINE_CLKSEL(dpll_usb_m2_div, dpll_usb_ck, div31_1to31_rates); -static const struct clksel dpll_usb_m2_div[] = { - { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; +DEFINE_CLOCK(dpll_usb_m2_ck, dpll_usb_ck, CLOCK_OPS_DPLL(), + CLOCK_CLKSEL(dpll_usb_m2_div, + CM_DIV_M2_DPLL_USB, DPLL_CLKOUT_DIV_0_6)); -static struct clk dpll_usb_m2_ck = { - .name = "dpll_usb_m2_ck", - .parent = &dpll_usb_ck, - .clksel = dpll_usb_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLKSEL2(ducati_clk_mux_sel, div_core_ck, dpll_per_m6x2_ck); -static const struct clksel ducati_clk_mux_sel[] = { - { .parent = &div_core_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; +DEFINE_CLOCK(ducati_clk_mux_ck, div_core_ck, + CLOCK_CLKSEL_INIT(ducati_clk_mux_sel, + CM_CLKSEL_DUCATI_ISS_ROOT, CLKSEL_0_0)); -static struct clk ducati_clk_mux_ck = { - .name = "ducati_clk_mux_ck", - .parent = &div_core_ck, - .clksel = ducati_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; +DEFINE_CLOCK(func_12m_fclk, dpll_per_m2x2_ck, CLOCK_RECALC_FIXED(16)); -static struct clk func_12m_fclk = { - .name = "func_12m_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 16, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLOCK(func_24m_clk, dpll_per_m2_ck, CLOCK_RECALC_FIXED(4)); -static struct clk func_24m_clk = { - .name = "func_24m_clk", - .parent = &dpll_per_m2_ck, - .ops = &clkops_null, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLOCK(func_24mc_fclk, dpll_per_m2x2_ck, CLOCK_RECALC_FIXED(8)); -static struct clk func_24mc_fclk = { - .name = "func_24mc_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 8, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLKSEL_RATE2(4to8, 4, 8); -static const struct clksel_rate div2_4to8_rates[] = { - { .div = 4, .val = 0, .flags = RATE_IN_4430 }, - { .div = 8, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +DEFINE_CLKSEL(func_48m_fclk_div, dpll_per_m2x2_ck, div2_4to8_rates); -static const struct clksel func_48m_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, - { .parent = NULL }, -}; +DEFINE_CLOCK(func_48m_fclk, dpll_per_m2x2_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(func_48m_fclk_div, CM_SCALE_FCLK, SCALE_FCLK)); -static struct clk func_48m_fclk = { - .name = "func_48m_fclk", - .parent = &dpll_per_m2x2_ck, - .clksel = func_48m_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(func_48mc_fclk, dpll_per_m2x2_ck, CLOCK_RECALC_FIXED(4)); -static struct clk func_48mc_fclk = { - .name = "func_48mc_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLKSEL_RATE2(2to4, 2, 4); -static const struct clksel_rate div2_2to4_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_4430 }, - { .div = 4, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +DEFINE_CLKSEL(func_64m_fclk_div, dpll_per_m4x2_ck, div2_2to4_rates); -static const struct clksel func_64m_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, - { .parent = NULL }, -}; +DEFINE_CLOCK(func_64m_fclk, dpll_per_m4x2_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(func_64m_fclk_div, CM_SCALE_FCLK, SCALE_FCLK)); -static struct clk func_64m_fclk = { - .name = "func_64m_fclk", - .parent = &dpll_per_m4x2_ck, - .clksel = func_64m_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel func_96m_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(func_96m_fclk_div, dpll_per_m2x2_ck, div2_2to4_rates); -static struct clk func_96m_fclk = { - .name = "func_96m_fclk", - .parent = &dpll_per_m2x2_ck, - .clksel = func_96m_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(func_96m_fclk, dpll_per_m2x2_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(func_96m_fclk_div, CM_SCALE_FCLK, SCALE_FCLK)); -static const struct clksel hsmmc6_fclk_sel[] = { - { .parent = &func_64m_fclk, .rates = div_1_0_rates }, - { .parent = &func_96m_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL2(hsmmc6_fclk_sel, func_64m_fclk, func_96m_fclk); -static struct clk hsmmc6_fclk = { - .name = "hsmmc6_fclk", - .parent = &func_64m_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK(hsmmc6_fclk, func_64m_fclk, + CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT()); -static const struct clksel_rate div2_1to8_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 8, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; +DEFINE_CLKSEL_RATE2(1to8, 1, 8); -static const struct clksel init_60m_fclk_div[] = { - { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(init_60m_fclk_div, dpll_usb_m2_ck, div2_1to8_rates); -static struct clk init_60m_fclk = { - .name = "init_60m_fclk", - .parent = &dpll_usb_m2_ck, - .clksel = init_60m_fclk_div, - .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(init_60m_fclk, dpll_usb_m2_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(init_60m_fclk_div, CM_CLKSEL_USB_60MHZ, CLKSEL_0_0)); -static const struct clksel l3_div_div[] = { - { .parent = &div_core_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(l3_div_div, div_core_ck, div2_1to2_rates); -static struct clk l3_div_ck = { - .name = "l3_div_ck", - .parent = &div_core_ck, - .clksel = l3_div_div, - .clksel_reg = OMAP4430_CM_CLKSEL_CORE, - .clksel_mask = OMAP4430_CLKSEL_L3_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(l3_div_ck, div_core_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(l3_div_div, CM_CLKSEL_CORE, CLKSEL_L3)); -static const struct clksel l4_div_div[] = { - { .parent = &l3_div_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(l4_div_div, l3_div_ck, div2_1to2_rates); -static struct clk l4_div_ck = { - .name = "l4_div_ck", - .parent = &l3_div_ck, - .clksel = l4_div_div, - .clksel_reg = OMAP4430_CM_CLKSEL_CORE, - .clksel_mask = OMAP4430_CLKSEL_L4_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(l4_div_ck, l3_div_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(l4_div_div, CM_CLKSEL_CORE, CLKSEL_L4)); -static struct clk lp_clk_div_ck = { - .name = "lp_clk_div_ck", - .parent = &dpll_abe_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 16, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLOCK(lp_clk_div_ck, dpll_abe_m2x2_ck, CLOCK_RECALC_FIXED(16)); -static const struct clksel l4_wkup_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL2(l4_wkup_clk_mux_sel, sys_clkin_ck, lp_clk_div_ck); -static struct clk l4_wkup_clk_mux_ck = { - .name = "l4_wkup_clk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = l4_wkup_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; +DEFINE_CLOCK(l4_wkup_clk_mux_ck, sys_clkin_ck, + CLOCK_CLKSEL_INIT(l4_wkup_clk_mux_sel, + CM_L4_WKUP_CLKSEL, CLKSEL_0_0)); -static const struct clksel per_abe_nc_fclk_div[] = { - { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(per_abe_nc_fclk_div, dpll_abe_m2_ck, div2_1to2_rates); -static struct clk per_abe_nc_fclk = { - .name = "per_abe_nc_fclk", - .parent = &dpll_abe_m2_ck, - .clksel = per_abe_nc_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(per_abe_nc_fclk, dpll_abe_m2_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(per_abe_nc_fclk_div, CM_SCALE_FCLK, SCALE_FCLK)); -static const struct clksel mcasp2_fclk_sel[] = { - { .parent = &func_96m_fclk, .rates = div_1_0_rates }, - { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL2(mcasp2_fclk_sel, func_96m_fclk, per_abe_nc_fclk); -static struct clk mcasp2_fclk = { - .name = "mcasp2_fclk", - .parent = &func_96m_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK(mcasp2_fclk, func_96m_fclk, + CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT()); -static struct clk mcasp3_fclk = { - .name = "mcasp3_fclk", - .parent = &func_96m_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK(mcasp3_fclk, func_96m_fclk, + CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT()); -static struct clk ocp_abe_iclk = { - .name = "ocp_abe_iclk", - .parent = &aess_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK(ocp_abe_iclk, aess_fclk, + CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT()); -static struct clk per_abe_24m_fclk = { - .name = "per_abe_24m_fclk", - .parent = &dpll_abe_m2_ck, - .ops = &clkops_null, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, -}; +DEFINE_CLOCK(per_abe_24m_fclk, dpll_abe_m2_ck, CLOCK_RECALC_FIXED(4)); -static const struct clksel pmd_stm_clock_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, - { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL3(pmd_stm_clock_mux_sel, + sys_clkin_ck, dpll_core_m6x2_ck, tie_low_clock_ck); -static struct clk pmd_stm_clock_mux_ck = { - .name = "pmd_stm_clock_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK(pmd_stm_clock_mux_ck, sys_clkin_ck, + CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT()); -static struct clk pmd_trace_clk_mux_ck = { - .name = "pmd_trace_clk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK(pmd_trace_clk_mux_ck, sys_clkin_ck, + CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT()); -static const struct clksel syc_clk_div_div[] = { - { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(syc_clk_div_div, sys_clkin_ck, div2_1to2_rates); -static struct clk syc_clk_div_ck = { - .name = "syc_clk_div_ck", - .parent = &sys_clkin_ck, - .clksel = syc_clk_div_div, - .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; +DEFINE_CLOCK(syc_clk_div_ck, sys_clkin_ck, CLOCK_OPS_NULL(), + CLOCK_CLKSEL(syc_clk_div_div, CM_ABE_DSS_SYS_CLKSEL, CLKSEL_0_0)); /* Leaf clocks controlled by modules */ -static struct clk aes1_fck = { - .name = "aes1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(aes1_fck, l3_div_ck, l4_secure_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT_SW(CM_L4SEC_AES1)); -static struct clk aes2_fck = { - .name = "aes2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(aes2_fck, l3_div_ck, l4_secure_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT_SW(CM_L4SEC_AES2)); -static struct clk aess_fck = { - .name = "aess_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &aess_fclk, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(aess_fck, aess_fclk, abe_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT_SW(CM1_ABE_AESS)); -static struct clk bandgap_fclk = { - .name = "bandgap_fclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(bandgap_fclk, sys_32k_ck, l4_wkup_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT(CM_L4SEC_AES2, OPTFCLKEN_BGAP_32K)); -static struct clk des3des_fck = { - .name = "des3des_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(des3des_fck, l4_div_ck, l4_secure_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT_SW(CM_L4SEC_DES3DES)); -static const struct clksel dmic_sync_mux_sel[] = { - { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, - { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, - { .parent = &func_24m_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL3(dmic_sync_mux_sel, + abe_24m_fclk, syc_clk_div_ck, func_24m_clk); -static struct clk dmic_sync_mux_ck = { - .name = "dmic_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; +DEFINE_CLOCK(dmic_sync_mux_ck, abe_24m_fclk, + CLOCK_CLKSEL_INIT(dmic_sync_mux_sel, + CM1_ABE_DMIC_CLKCTRL, CLKSEL_INTERNAL_SOURCE)); -static const struct clksel func_dmic_abe_gfclk_sel[] = { - { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL3(func_dmic_abe_gfclk_sel, + dmic_sync_mux_ck, pad_clks_ck, slimbus_clk); /* Merged func_dmic_abe_gfclk into dmic */ -static struct clk dmic_fck = { - .name = "dmic_fck", - .parent = &dmic_sync_mux_ck, - .clksel = func_dmic_abe_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; +DEFINE_CLOCK_DM(dmic_fck, dmic_sync_mux_ck, abe_clkdm, + CLOCK_CLKSEL_INIT_SW(func_dmic_abe_gfclk_sel, + CM1_ABE_DMIC, CLKSEL_SOURCE)); -static struct clk dsp_fck = { - .name = "dsp_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "tesla_clkdm", - .parent = &dpll_iva_m4x2_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(dsp_fck, dpll_iva_m4x2_ck, tesla_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT_HW(CM_TESLA_TESLA)); -static struct clk dss_sys_clk = { - .name = "dss_sys_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &syc_clk_div_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(dss_sys_clk, syc_clk_div_ck, l3_dss_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_SYS_CLK)); -static struct clk dss_tv_clk = { - .name = "dss_tv_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &extalt_clkin_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(dss_tv_clk, extalt_clkin_ck, l3_dss_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_TV_CLK)); -static struct clk dss_dss_clk = { - .name = "dss_dss_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &dpll_per_m5x2_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(dss_dss_clk, dpll_per_m5x2_ck, l3_dss_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_DSSCLK)); -static struct clk dss_48mhz_clk = { - .name = "dss_48mhz_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(dss_48mhz_clk, func_48mc_fclk, l3_dss_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_48MHZ_CLK)); -static struct clk dss_fck = { - .name = "dss_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_dss_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(dss_fck, l3_div_ck, l3_dss_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT_SW(CM_DSS_DSS)); -static struct clk efuse_ctrl_cust_fck = { - .name = "efuse_ctrl_cust_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_cefuse_clkdm", - .parent = &sys_clkin_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(efuse_ctrl_cust_fck, sys_clkin_ck, l4_cefuse_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT_SW(CM_CEFUSE_CEFUSE)); -static struct clk emif1_fck = { - .name = "emif1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .flags = ENABLE_ON_INIT, - .clkdm_name = "l3_emif_clkdm", - .parent = &ddrphy_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(emif1_fck, ddrphy_ck, l3_emif_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT_HW(CM_MEMIF_EMIF_1), + CLOCK_FLAGS_ENABLE()); -static struct clk emif2_fck = { - .name = "emif2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .flags = ENABLE_ON_INIT, - .clkdm_name = "l3_emif_clkdm", - .parent = &ddrphy_ck, - .recalc = &followparent_recalc, -}; +DEFINE_CLOCK_DM(emif2_fck, ddrphy_ck, l3_emif_clkdm, + CLOCK_RECALC_FOLLOWPARENT(), + CLOCK_OPS_DFLT_HW(CM_MEMIF_EMIF_2), + CLOCK_FLAGS_ENABLE()); -static const struct clksel fdif_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; +DEFINE_CLKSEL(fdif_fclk_div, dpll_per_m4x2_ck, div3_1to4_rates); /* Merged fdif_fclk into fdif */ static struct clk fdif_fck = {