From patchwork Fri May 20 15:14:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 803992 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p4KFFeKx010097 for ; Fri, 20 May 2011 15:15:40 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933713Ab1ETPPi (ORCPT ); Fri, 20 May 2011 11:15:38 -0400 Received: from na3sys009aog104.obsmtp.com ([74.125.149.73]:45951 "EHLO na3sys009aog104.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933413Ab1ETPPi (ORCPT ); Fri, 20 May 2011 11:15:38 -0400 Received: from mail-wy0-f177.google.com ([74.125.82.177]) (using TLSv1) by na3sys009aob104.postini.com ([74.125.148.12]) with SMTP ID DSNKTdaFmaJELJwsHCZ408DYhyfsHZ5wtzL2@postini.com; Fri, 20 May 2011 08:15:37 PDT Received: by wyb28 with SMTP id 28so3404851wyb.8 for ; Fri, 20 May 2011 08:15:35 -0700 (PDT) Received: by 10.216.81.203 with SMTP id m53mr794998wee.9.1305904535855; Fri, 20 May 2011 08:15:35 -0700 (PDT) Received: from localhost ([192.91.60.233]) by mx.google.com with ESMTPS id a82sm1902207wep.6.2011.05.20.08.15.33 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 20 May 2011 08:15:34 -0700 (PDT) From: Kevin Hilman To: linux-omap@vger.kernel.org, Grant Likely , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/14] GPIO: OMAP: convert MPUIO IRQ over to generic irq_chip Date: Fri, 20 May 2011 17:14:53 +0200 Message-Id: <1305904497-26013-11-git-send-email-khilman@ti.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1305904497-26013-1-git-send-email-khilman@ti.com> References: <1305904497-26013-1-git-send-email-khilman@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 20 May 2011 15:15:40 +0000 (UTC) MPUIO banks have their own dedicated IRQ chip interface, separate from the "normal" GPIO banks. Convert the MPUIO IRQ chip over to using the new generic IRQ chip interface. Signed-off-by: Kevin Hilman --- drivers/gpio/gpio_omap.c | 74 ++++++++++++++++++--------------------------- 1 files changed, 30 insertions(+), 44 deletions(-) diff --git a/drivers/gpio/gpio_omap.c b/drivers/gpio/gpio_omap.c index 6bb3785..d84cc95 100644 --- a/drivers/gpio/gpio_omap.c +++ b/drivers/gpio/gpio_omap.c @@ -875,45 +875,8 @@ static struct irq_chip gpio_irq_chip = { #ifdef CONFIG_ARCH_OMAP1 -/* MPUIO uses the always-on 32k clock */ - -static void mpuio_ack_irq(struct irq_data *d) -{ - /* The ISR is reset automatically, so do nothing here. */ -} - -static void mpuio_mask_irq(struct irq_data *d) -{ - unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); - struct gpio_bank *bank = irq_data_get_irq_chip_data(d); - - _set_gpio_irqenable(bank, gpio, 0); -} - -static void mpuio_unmask_irq(struct irq_data *d) -{ - unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); - struct gpio_bank *bank = irq_data_get_irq_chip_data(d); - - _set_gpio_irqenable(bank, gpio, 1); -} - -static struct irq_chip mpuio_irq_chip = { - .name = "MPUIO", - .irq_ack = mpuio_ack_irq, - .irq_mask = mpuio_mask_irq, - .irq_unmask = mpuio_unmask_irq, - .irq_set_type = gpio_irq_type, -#ifdef CONFIG_ARCH_OMAP16XX - /* REVISIT: assuming only 16xx supports MPUIO wake events */ - .irq_set_wake = gpio_wake_enable, -#endif -}; - - #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) - #ifdef CONFIG_ARCH_OMAP16XX #include @@ -988,8 +951,6 @@ static inline void mpuio_init(void) {} #else -extern struct irq_chip mpuio_irq_chip; - #define bank_is_mpuio(bank) 0 static inline void mpuio_init(void) {} @@ -1189,6 +1150,30 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id) } } +static __init void +omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, + unsigned int num) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, + handle_simple_irq); + ct = gc->chip_types; + + /* NOTE: No ack required, reading IRQ status clears it. */ + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + ct->chip.irq_set_type = gpio_irq_type; + /* REVISIT: assuming only 16xx supports MPUIO wake events */ + if (cpu_is_omap16xx()) + ct->chip.irq_set_wake = gpio_wake_enable, + + ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; + irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); +} + static void __init omap_gpio_chip_init(struct gpio_bank *bank) { int j; @@ -1226,12 +1211,13 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank) j < bank->virtual_irq_start + bank->width; j++) { irq_set_lockdep_class(j, &gpio_lock_class); irq_set_chip_data(j, bank); - if (bank_is_mpuio(bank)) - irq_set_chip(j, &mpuio_irq_chip); - else + if (bank_is_mpuio(bank)) { + omap_mpuio_alloc_gc(bank, j, bank->width); + } else { irq_set_chip(j, &gpio_irq_chip); - irq_set_handler(j, handle_simple_irq); - set_irq_flags(j, IRQF_VALID); + irq_set_handler(j, handle_simple_irq); + set_irq_flags(j, IRQF_VALID); + } } irq_set_chained_handler(bank->irq, gpio_irq_handler); irq_set_handler_data(bank->irq, bank);