From patchwork Tue May 24 14:24:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tarun Kanti DebBarma X-Patchwork-Id: 812022 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p4OEPBbG011955 for ; Tue, 24 May 2011 14:25:12 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756109Ab1EXOZJ (ORCPT ); Tue, 24 May 2011 10:25:09 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:43512 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756092Ab1EXOZI (ORCPT ); Tue, 24 May 2011 10:25:08 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id p4OEP1po000719 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 24 May 2011 09:25:04 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p4OEP1R1028576; Tue, 24 May 2011 19:55:01 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Tue, 24 May 2011 19:55:01 +0530 Received: from localhost.localdomain ([172.24.190.106]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p4OEOsqK004036; Tue, 24 May 2011 19:55:00 +0530 (IST) From: Tarun Kanti DebBarma To: CC: , , , , Charulatha V , Tarun Kanti DebBarma Subject: [PATCH 15/15] OMAP: GPIO: clean omap_gpio_mod_init function Date: Tue, 24 May 2011 19:54:54 +0530 Message-ID: <1306247094-25372-16-git-send-email-tarun.kanti@ti.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1306247094-25372-1-git-send-email-tarun.kanti@ti.com> References: <1306247094-25372-1-git-send-email-tarun.kanti@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 24 May 2011 14:25:12 +0000 (UTC) From: Charulatha V With register offsets now defined for respective OMAP versions we can get rid of cpu_class_* checks. In addition, organized common initialization for the different OMAP silicon versions. Signed-off-by: Charulatha V Signed-off-by: Tarun Kanti DebBarma --- arch/arm/mach-omap1/gpio16xx.c | 1 + arch/arm/plat-omap/include/plat/gpio.h | 1 + drivers/gpio/gpio_omap.c | 74 +++++++++++++------------------- 3 files changed, 32 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c index 24f6cfa..e9f8abd 100644 --- a/arch/arm/mach-omap1/gpio16xx.c +++ b/arch/arm/mach-omap1/gpio16xx.c @@ -227,6 +227,7 @@ static int __init omap16xx_gpio_init(void) omap16xx_gpio_regs.wkupset = OMAP1610_GPIO_SET_WAKEUPENA; omap16xx_gpio_regs.edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1; omap16xx_gpio_regs.edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2; + omap16xx_gpio_regs.sysconfig = OMAP1610_GPIO_SYSCONFIG; for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) platform_device_register(omap16xx_gpio_dev[i]); diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index f82881c..ac45191 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -176,6 +176,7 @@ struct omap_gpio_dev_attr { struct omap_gpio_reg_offs { u16 revision; + u16 sysconfig; u16 direction; u16 datain; u16 dataout; diff --git a/drivers/gpio/gpio_omap.c b/drivers/gpio/gpio_omap.c index ebeb16e..3649c74 100644 --- a/drivers/gpio/gpio_omap.c +++ b/drivers/gpio/gpio_omap.c @@ -885,65 +885,51 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank) called = true; } -/* This lock class tells lockdep that GPIO irqs are in a different +/* + * This lock class tells lockdep that GPIO irqs are in a different * category than their parents, so it won't report false recursion. */ static struct lock_class_key gpio_lock_class; -/* TODO: Cleanup cpu_is_* checks */ static void omap_gpio_mod_init(struct gpio_bank *bank) { - if (cpu_class_is_omap2()) { - if (cpu_is_omap44xx()) { - __raw_writel(0xffffffff, bank->base + - OMAP4_GPIO_IRQSTATUSCLR0); - __raw_writel(0x00000000, bank->base + - OMAP4_GPIO_DEBOUNCENABLE); - /* Initialize interface clk ungated, module enabled */ - __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); - } else if (cpu_is_omap34xx()) { - __raw_writel(0x00000000, bank->base + - OMAP24XX_GPIO_IRQENABLE1); - __raw_writel(0xffffffff, bank->base + - OMAP24XX_GPIO_IRQSTATUS1); - __raw_writel(0x00000000, bank->base + - OMAP24XX_GPIO_DEBOUNCE_EN); + if (bank->width == 32) { + u32 l = 0; + + if (bank->regs->irqenable_inv) + l = ~l; + __raw_writel(l, bank->base + bank->regs->irqstatus); + __raw_writel(l, bank->base + bank->regs->irqenable); + + if (bank->regs->debounce_en != USHRT_MAX) + __raw_writel(l, bank->base + bank->regs->debounce_en); + + if (bank->regs->ctrl != USHRT_MAX) /* Initialize interface clk ungated, module enabled */ - __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); - } - } else if (cpu_class_is_omap1()) { - if (bank_is_mpuio(bank)) { - __raw_writew(0xffff, bank->base + - OMAP_MPUIO_GPIO_MASKIT / bank->stride); + __raw_writel(l, bank->base + bank->regs->ctrl); + + } else if (bank->width == 16) { + u16 l = 0; + + if (bank_is_mpuio(bank)) mpuio_init(bank); - } - if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { - __raw_writew(0xffff, bank->base - + OMAP1510_GPIO_INT_MASK); - __raw_writew(0x0000, bank->base - + OMAP1510_GPIO_INT_STATUS); - } - if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { - __raw_writew(0x0000, bank->base - + OMAP1610_GPIO_IRQENABLE1); - __raw_writew(0xffff, bank->base - + OMAP1610_GPIO_IRQSTATUS1); - __raw_writew(0x0014, bank->base - + OMAP1610_GPIO_SYSCONFIG); + if (bank->regs->irqenable_inv) + l = ~l; + + __raw_writew(l, bank->base + bank->regs->irqstatus); + __raw_writew(l, bank->base + bank->regs->irqenable); + + if (bank->regs->sysconfig != USHRT_MAX) { + /* set wakeup-enable and smart-idle */ + __raw_writew(0x14, bank->base + bank->regs->sysconfig); /* * Enable system clock for GPIO module. * The CAM_CLK_CTRL *is* really the right place. */ omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, - ULPD_CAM_CLK_CTRL); - } - if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { - __raw_writel(0xffffffff, bank->base - + OMAP7XX_GPIO_INT_MASK); - __raw_writel(0x00000000, bank->base - + OMAP7XX_GPIO_INT_STATUS); + ULPD_CAM_CLK_CTRL); } } }