From patchwork Sat Jun 4 19:03:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Cross X-Patchwork-Id: 849352 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p54J4nor024715 for ; Sat, 4 Jun 2011 19:04:49 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752243Ab1FDTEV (ORCPT ); Sat, 4 Jun 2011 15:04:21 -0400 Received: from smtp-out.google.com ([216.239.44.51]:55948 "EHLO smtp-out.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752155Ab1FDTEV (ORCPT ); Sat, 4 Jun 2011 15:04:21 -0400 Received: from kpbe16.cbf.corp.google.com (kpbe16.cbf.corp.google.com [172.25.105.80]) by smtp-out.google.com with ESMTP id p54J46Jn026854; Sat, 4 Jun 2011 12:04:06 -0700 Received: from walnut.mtv.corp.google.com (walnut.mtv.corp.google.com [172.18.102.62]) by kpbe16.cbf.corp.google.com with ESMTP id p54J447n013342; Sat, 4 Jun 2011 12:04:04 -0700 Received: by walnut.mtv.corp.google.com (Postfix, from userid 99897) id 364872578EC; Sat, 4 Jun 2011 12:04:04 -0700 (PDT) From: Colin Cross To: linux-omap@vger.kernel.org Cc: Colin Cross , Tony Lindgren , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: omap4: gpio: fix setting IRQWAKEN bits Date: Sat, 4 Jun 2011 12:03:59 -0700 Message-Id: <1307214239-16316-1-git-send-email-ccross@android.com> X-Mailer: git-send-email 1.7.4.1 X-System-Of-Record: true Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Sat, 04 Jun 2011 19:04:49 +0000 (UTC) Setting the IRQWAKEN bit was overwriting previous IRQWAKEN bits, causing only the last bit set to take effect, resulting in lost wakeups when the GPIO controller is in idle. Replace direct writes to IRQWAKEN with writes to SETWKUENA and CLEARWKUEN. Signed-off-by: Colin Cross Acked-by: Santosh Shilimkar --- arch/arm/plat-omap/gpio.c | 14 +++++--------- 1 files changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index c985652..23ac7b6 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -539,7 +539,6 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, { void __iomem *base = bank->base; u32 gpio_bit = 1 << gpio; - u32 val; if (cpu_is_omap44xx()) { MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, @@ -563,14 +562,11 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { if (cpu_is_omap44xx()) { if (trigger != 0) - __raw_writel(1 << gpio, bank->base+ - OMAP4_GPIO_IRQWAKEN0); - else { - val = __raw_readl(bank->base + - OMAP4_GPIO_IRQWAKEN0); - __raw_writel(val & (~(1 << gpio)), bank->base + - OMAP4_GPIO_IRQWAKEN0); - } + __raw_writel(gpio_bit, + bank->base + OMAP4_GPIO_SETWKUENA); + else + __raw_writel(gpio_bit, + bank->base + OMAP4_GPIO_CLEARWKUENA); } else { /* * GPIO wakeup request can only be generated on edge