From patchwork Mon Jun 6 20:38:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Cross X-Patchwork-Id: 853752 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p56Kd861027478 for ; Mon, 6 Jun 2011 20:39:08 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756071Ab1FFUil (ORCPT ); Mon, 6 Jun 2011 16:38:41 -0400 Received: from smtp-out.google.com ([216.239.44.51]:56514 "EHLO smtp-out.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751965Ab1FFUik (ORCPT ); Mon, 6 Jun 2011 16:38:40 -0400 Received: from kpbe12.cbf.corp.google.com (kpbe12.cbf.corp.google.com [172.25.105.76]) by smtp-out.google.com with ESMTP id p56KcSB3012825; Mon, 6 Jun 2011 13:38:28 -0700 Received: from walnut.mtv.corp.google.com (walnut.mtv.corp.google.com [172.18.102.62]) by kpbe12.cbf.corp.google.com with ESMTP id p56KcQon009354; Mon, 6 Jun 2011 13:38:26 -0700 Received: by walnut.mtv.corp.google.com (Postfix, from userid 99897) id 1D1012578F4; Mon, 6 Jun 2011 13:38:26 -0700 (PDT) From: Colin Cross To: linux-omap@vger.kernel.org Cc: Santosh Shilimkar , tarun.kanti@ti.com, linux-arm-kernel@lists.infradead.org, Colin Cross , Grant Likely , linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] ARM: omap4: gpio: fix setting IRQWAKEN bits Date: Mon, 6 Jun 2011 13:38:17 -0700 Message-Id: <1307392698-21170-1-git-send-email-ccross@android.com> X-Mailer: git-send-email 1.7.4.1 X-System-Of-Record: true Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Mon, 06 Jun 2011 20:39:08 +0000 (UTC) Setting the IRQWAKEN bit was overwriting previous IRQWAKEN bits, causing only the last bit set to take effect, resulting in lost wakeups when the GPIO controller is in idle. Replace direct writes to IRQWAKEN with MOD_REG_BIT calls to perform a read-modify-write on the register. Signed-off-by: Colin Cross Acked-by: Grant Likely --- drivers/gpio/gpio-omap.c | 12 ++---------- 1 files changed, 2 insertions(+), 10 deletions(-) Santosh, I left your Acked-by off this patch because I changed the register access to match the OMAP4 TRM. diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 6c51191..8ba6957 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -432,7 +432,6 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, { void __iomem *base = bank->base; u32 gpio_bit = 1 << gpio; - u32 val; if (cpu_is_omap44xx()) { MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, @@ -455,15 +454,8 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, } if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { if (cpu_is_omap44xx()) { - if (trigger != 0) - __raw_writel(1 << gpio, bank->base+ - OMAP4_GPIO_IRQWAKEN0); - else { - val = __raw_readl(bank->base + - OMAP4_GPIO_IRQWAKEN0); - __raw_writel(val & (~(1 << gpio)), bank->base + - OMAP4_GPIO_IRQWAKEN0); - } + MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit, + trigger != 0); } else { /* * GPIO wakeup request can only be generated on edge