From patchwork Tue Jun 7 02:16:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 855182 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p572Jbb3006527 for ; Tue, 7 Jun 2011 02:19:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756500Ab1FGCTh (ORCPT ); Mon, 6 Jun 2011 22:19:37 -0400 Received: from na3sys009aog113.obsmtp.com ([74.125.149.209]:46855 "EHLO na3sys009aog113.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754812Ab1FGCTg (ORCPT ); Mon, 6 Jun 2011 22:19:36 -0400 Received: from mail-gw0-f41.google.com ([74.125.83.41]) (using TLSv1) by na3sys009aob113.postini.com ([74.125.148.12]) with SMTP ID DSNKTe2Kt/RBkCGl87P8uq7EGqdCqumx6TDm@postini.com; Mon, 06 Jun 2011 19:19:36 PDT Received: by mail-gw0-f41.google.com with SMTP id a12so1697085gwa.28 for ; Mon, 06 Jun 2011 19:19:35 -0700 (PDT) Received: by 10.91.163.4 with SMTP id q4mr4969127ago.96.1307412985772; Mon, 06 Jun 2011 19:16:25 -0700 (PDT) Received: from localhost (dragon.ti.com [192.94.94.33]) by mx.google.com with ESMTPS id x32sm3723204anx.32.2011.06.06.19.16.23 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 06 Jun 2011 19:16:24 -0700 (PDT) From: Nishanth Menon To: linux-omap Cc: kevin , Nishanth Menon Subject: [pm-wip/voltdm_nm][PATCH 04/10] OMAP4: PM: VC: allow channels use of default channel volt_reg_addr Date: Mon, 6 Jun 2011 21:16:07 -0500 Message-Id: <1307412972-25854-5-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1307412972-25854-1-git-send-email-nm@ti.com> References: <1307412972-25854-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 07 Jun 2011 02:19:38 +0000 (UTC) OMAP4's PRM_VC_CFG_CHANNEL register allows for flexibility of configuring for various PMIC configurations. In combinations where we'd like to use the default VC channel's voltage_reg address in a particular non-default VC channel, we allow the use of USE_DEFAULT_CHANNEL_I2C_PARAM. Since 0 is a valid register address, we need to increase the size of reg storage for the flag. Depending on the PMIC and platform used, this can be populated on the PMIC's datastructure and percolates to VC's configuration. Signed-off-by: Nishanth Menon --- arch/arm/mach-omap2/vc.c | 17 ++++++++++------- arch/arm/mach-omap2/vc.h | 2 +- arch/arm/mach-omap2/voltage.h | 4 ++-- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 6017c70..53a16cc 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -310,10 +310,11 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) vc->setup_time = voltdm->pmic->volt_setup_time; if ((vc->flags & OMAP_VC_CHANNEL_DEFAULT) && - (vc->i2c_slave_addr == USE_DEFAULT_CHANNEL_I2C_PARAM)) { + ((vc->i2c_slave_addr == USE_DEFAULT_CHANNEL_I2C_PARAM) || + (vc->volt_reg_addr == USE_DEFAULT_CHANNEL_I2C_PARAM))) { pr_err("%s: voltdm %s: default channel " - "bad config-sa=%2x ?\n", __func__, voltdm->name, - vc->i2c_slave_addr); + "bad config-sa=%2x vol=%2x?\n", __func__, voltdm->name, + vc->i2c_slave_addr, vc->volt_reg_addr); return; } @@ -328,10 +329,12 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) /* * Configure the PMIC register addresses. */ - voltdm->rmw(vc->smps_volra_mask, - vc->volt_reg_addr << __ffs(vc->smps_volra_mask), - vc->common->smps_volra_reg); - vc->cfg_channel |= vc_cfg_bits->rav; + if (vc->volt_reg_addr != USE_DEFAULT_CHANNEL_I2C_PARAM) { + voltdm->rmw(vc->smps_volra_mask, + vc->volt_reg_addr << __ffs(vc->smps_volra_mask), + vc->common->smps_volra_reg); + vc->cfg_channel |= vc_cfg_bits->rav; + } if (vc->cmd_reg_addr) { voltdm->rmw(vc->smps_cmdra_mask, diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h index 22c0060..310368f 100644 --- a/arch/arm/mach-omap2/vc.h +++ b/arch/arm/mach-omap2/vc.h @@ -78,7 +78,7 @@ struct omap_vc_channel { /* channel state */ u16 i2c_slave_addr; - u8 volt_reg_addr; + u16 volt_reg_addr; u8 cmd_reg_addr; u8 cfg_channel; u16 setup_time; diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index 1732258..75f3557 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -114,7 +114,7 @@ struct omap_volt_data { * channel is MPU, all other domains such as IVA/CORE, could optionally * link their i2c reg configuration to use MPU channel's configuration if * required. To do this, mark in the PMIC structure's - * i2c_slave_addr with this macro. + * i2c_slave_addr, volt_reg_addr with this macro. */ #define USE_DEFAULT_CHANNEL_I2C_PARAM 0x8000 @@ -142,7 +142,7 @@ struct omap_voltdm_pmic { u8 vp_vddmax; u8 vp_timeout_us; u16 i2c_slave_addr; - u8 volt_reg_addr; + u16 volt_reg_addr; u8 cmd_reg_addr; bool i2c_high_speed; u8 i2c_mcode;