From patchwork Tue Jun 7 02:16:08 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 855132 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p572FeQT025132 for ; Tue, 7 Jun 2011 02:18:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756763Ab1FGCQa (ORCPT ); Mon, 6 Jun 2011 22:16:30 -0400 Received: from na3sys009aog112.obsmtp.com ([74.125.149.207]:35146 "EHLO na3sys009aog112.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756655Ab1FGCQ3 (ORCPT ); Mon, 6 Jun 2011 22:16:29 -0400 Received: from mail-yi0-f42.google.com ([209.85.218.42]) (using TLSv1) by na3sys009aob112.postini.com ([74.125.148.12]) with SMTP ID DSNKTe2J/QjOaC4J+Z/9PiomGx7xc2U4GXsa@postini.com; Mon, 06 Jun 2011 19:16:29 PDT Received: by mail-yi0-f42.google.com with SMTP id 16so826635yie.15 for ; Mon, 06 Jun 2011 19:16:29 -0700 (PDT) Received: by 10.91.201.4 with SMTP id d4mr5187855agq.41.1307412988906; Mon, 06 Jun 2011 19:16:28 -0700 (PDT) Received: from localhost (dragon.ti.com [192.94.94.33]) by mx.google.com with ESMTPS id x14sm3726469ani.7.2011.06.06.19.16.27 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 06 Jun 2011 19:16:27 -0700 (PDT) From: Nishanth Menon To: linux-omap Cc: kevin , Nishanth Menon Subject: [pm-wip/voltdm_nm][PATCH 05/10] OMAP4: PM: VC: allow channels use of default channel cmd_reg_addr Date: Mon, 6 Jun 2011 21:16:08 -0500 Message-Id: <1307412972-25854-6-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1307412972-25854-1-git-send-email-nm@ti.com> References: <1307412972-25854-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 07 Jun 2011 02:18:37 +0000 (UTC) OMAP4's PRM_VC_CFG_CHANNEL register allows for flexibility of configuring for various PMIC configurations. In combinations where we'd like to use the default VC channel's cmd_reg address in a particular non-default VC channel, we allow the use of USE_DEFAULT_CHANNEL_I2C_PARAM. Since 0 is a valid register address, we need to increase the size of reg storage for the flag. Depending on the PMIC and platform used, this can be populated on the PMIC's datastructure and percolates to VC's configuration. Signed-off-by: Nishanth Menon --- arch/arm/mach-omap2/vc.c | 8 +++++--- arch/arm/mach-omap2/vc.h | 2 +- arch/arm/mach-omap2/voltage.h | 4 ++-- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 53a16cc..0af99c8 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -311,10 +311,12 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) if ((vc->flags & OMAP_VC_CHANNEL_DEFAULT) && ((vc->i2c_slave_addr == USE_DEFAULT_CHANNEL_I2C_PARAM) || + (vc->cmd_reg_addr == USE_DEFAULT_CHANNEL_I2C_PARAM) || (vc->volt_reg_addr == USE_DEFAULT_CHANNEL_I2C_PARAM))) { pr_err("%s: voltdm %s: default channel " - "bad config-sa=%2x vol=%2x?\n", __func__, voltdm->name, - vc->i2c_slave_addr, vc->volt_reg_addr); + "bad config-sa=%2x vol=%2x, cmd=%2x?\n", __func__, + voltdm->name, vc->i2c_slave_addr, vc->volt_reg_addr, + vc->cmd_reg_addr); return; } @@ -336,7 +338,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) vc->cfg_channel |= vc_cfg_bits->rav; } - if (vc->cmd_reg_addr) { + if (vc->cmd_reg_addr != USE_DEFAULT_CHANNEL_I2C_PARAM) { voltdm->rmw(vc->smps_cmdra_mask, vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), vc->common->smps_cmdra_reg); diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h index 310368f..3b25d9c 100644 --- a/arch/arm/mach-omap2/vc.h +++ b/arch/arm/mach-omap2/vc.h @@ -79,7 +79,7 @@ struct omap_vc_channel { /* channel state */ u16 i2c_slave_addr; u16 volt_reg_addr; - u8 cmd_reg_addr; + u16 cmd_reg_addr; u8 cfg_channel; u16 setup_time; bool i2c_high_speed; diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index 75f3557..0a4232f 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -114,7 +114,7 @@ struct omap_volt_data { * channel is MPU, all other domains such as IVA/CORE, could optionally * link their i2c reg configuration to use MPU channel's configuration if * required. To do this, mark in the PMIC structure's - * i2c_slave_addr, volt_reg_addr with this macro. + * i2c_slave_addr, volt_reg_addr,cmd_reg_addr with this macro. */ #define USE_DEFAULT_CHANNEL_I2C_PARAM 0x8000 @@ -143,7 +143,7 @@ struct omap_voltdm_pmic { u8 vp_timeout_us; u16 i2c_slave_addr; u16 volt_reg_addr; - u8 cmd_reg_addr; + u16 cmd_reg_addr; bool i2c_high_speed; u8 i2c_mcode; unsigned long (*vsel_to_uv) (const u8 vsel);