From patchwork Thu Jun 9 10:54:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 863902 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p59Asem2004695 for ; Thu, 9 Jun 2011 10:54:41 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755004Ab1FIKyj (ORCPT ); Thu, 9 Jun 2011 06:54:39 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:49955 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757233Ab1FIKye (ORCPT ); Thu, 9 Jun 2011 06:54:34 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p59AsKlT012286 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 9 Jun 2011 05:54:22 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p59AsHUj018053; Thu, 9 Jun 2011 16:24:20 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Thu, 9 Jun 2011 16:24:18 +0530 Received: from linfarm476.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p59AsGJa017570; Thu, 9 Jun 2011 16:24:16 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id p59AsGOu028769; Thu, 9 Jun 2011 16:24:16 +0530 Received: (from a0131687@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id p59AsGZK028767; Thu, 9 Jun 2011 16:24:16 +0530 From: Rajendra Nayak To: CC: , , , , , Rajendra Nayak Subject: [PATCH 8/8] OMAP: clock: Enable clockdomain only for optional clocks Date: Thu, 9 Jun 2011 16:24:13 +0530 Message-ID: <1307616853-28395-9-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1307616853-28395-8-git-send-email-rnayak@ti.com> References: <1307616853-28395-1-git-send-email-rnayak@ti.com> <1307616853-28395-2-git-send-email-rnayak@ti.com> <1307616853-28395-3-git-send-email-rnayak@ti.com> <1307616853-28395-4-git-send-email-rnayak@ti.com> <1307616853-28395-5-git-send-email-rnayak@ti.com> <1307616853-28395-6-git-send-email-rnayak@ti.com> <1307616853-28395-7-git-send-email-rnayak@ti.com> <1307616853-28395-8-git-send-email-rnayak@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 09 Jun 2011 10:54:41 +0000 (UTC) Optional clocks have a requirement to have the clockdomain force enabled (SW_WKUP) before the optional clock itself is enabled. Since optional clocks are currently handled directly by drivers using the clock framework, this needs to be handled at the clock framework. This sequence is already handled in the omap_hwmod framework for the essential/main clocks. Signed-off-by: Rajendra Nayak --- arch/arm/mach-omap2/clock.c | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 2828d29..ff71ff7 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -286,6 +286,7 @@ void omap2_clk_disable(struct clk *clk) int omap2_clk_enable(struct clk *clk) { int ret; + int hwsup = 0; pr_debug("clock: %s: incrementing usecount\n", clk->name); @@ -304,6 +305,17 @@ int omap2_clk_enable(struct clk *clk) goto oce_err1; } } + /* + * TODO: This is needed here only as long as drivers use + * clock framework to enable optional clocks. For all the + * essential clocks, this sequence is handled in the + * omap_hwmod framework. + */ + /* Enable the clockdomain, if its an optional clock */ + if ((clk->flags & CLOCK_OPTCLK) && (clk->clkdm)) { + hwsup = clkdm_is_idle(clk->clkdm); + clkdm_wakeup(clk->clkdm); + } if (clk->ops && clk->ops->enable) { trace_clock_enable(clk->name, 1, smp_processor_id()); @@ -315,6 +327,9 @@ int omap2_clk_enable(struct clk *clk) } } + if ((clk->flags & CLOCK_OPTCLK) && (clk->clkdm) && hwsup) + clkdm_allow_idle(clk->clkdm); + return 0; oce_err2: