From patchwork Mon Jun 27 16:33:08 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 921642 X-Patchwork-Delegate: b-cousson@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p5RGY13d000823 for ; Mon, 27 Jun 2011 16:34:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752804Ab1F0QeC (ORCPT ); Mon, 27 Jun 2011 12:34:02 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:40081 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752765Ab1F0Qd7 (ORCPT ); Mon, 27 Jun 2011 12:33:59 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p5RGXvBa020683 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 27 Jun 2011 11:33:57 -0500 Received: from dlep26.itg.ti.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id p5RGXvUt023770; Mon, 27 Jun 2011 11:33:57 -0500 (CDT) Received: from dlee73.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id p5RGXvvm017388; Mon, 27 Jun 2011 11:33:57 -0500 (CDT) Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE73.ent.ti.com (157.170.170.88) with Microsoft SMTP Server id 8.3.106.1; Mon, 27 Jun 2011 11:33:56 -0500 Received: from localhost.localdomain (lncpu04.tif.ti.com [137.167.102.15]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id p5RGXlLQ003346; Mon, 27 Jun 2011 11:33:55 -0500 From: Benoit Cousson To: , CC: santosh.shilimkar@ti.com, linux-omap@vger.kernel.org, Benoit Cousson , Tomi Valkeinen Subject: [PATCH 4/7] OMAP4: hwmod data: Replace main_clk with the real input clock Date: Mon, 27 Jun 2011 18:33:08 +0200 Message-ID: <1309192391-12410-5-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1309192391-12410-1-git-send-email-b-cousson@ti.com> References: <1309192391-12410-1-git-send-email-b-cousson@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 27 Jun 2011 16:34:04 +0000 (UTC) Previously, main_clk was a fake clock node that was accessing the PRCM modulemode register. Since the module mode is directly controlled by the hwmod fmwk, these fake clock node are not needed anymore. The hwmod main_clk will point directly to the input clock node if applicable. For example, some IPs, like the GPIOs, do not have any functional clock and are using only the iclk. In that case, the main_clk field will be empty. In the case of the DSS, we can now consider all the optional clock as main clock. That will simplify greatly the driver management and the integration with hwmod. Signed-off-by: Benoit Cousson Cc: Tomi Valkeinen Cc: Paul Walmsley Cc: Rajendra Nayak --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 111 +++++++++++++--------------- 1 files changed, 51 insertions(+), 60 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index e10d3f7..5c196a1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -814,7 +814,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs), .sdma_reqs = omap44xx_aess_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs), - .main_clk = "aess_fck", + .main_clk = "aess_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, @@ -1086,7 +1086,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs), .sdma_reqs = omap44xx_dmic_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs), - .main_clk = "dmic_fck", + .main_clk = "func_dmic_abe_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, @@ -1172,7 +1172,7 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs), .rst_lines = omap44xx_dsp_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), - .main_clk = "dsp_fck", + .main_clk = "dpll_iva_m4x2_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, @@ -1263,7 +1263,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = { .name = "dss_core", .class = &omap44xx_dss_hwmod_class, .clkdm_name = "l3_dss_clkdm", - .main_clk = "dss_fck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, @@ -1363,7 +1362,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs), .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs), - .main_clk = "dss_fck", + .main_clk = "dss_dss_clk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, @@ -1456,7 +1455,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs), .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs), - .main_clk = "dss_fck", + .main_clk = "dss_sys_clk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, @@ -1528,7 +1527,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs), .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs), - .main_clk = "dss_fck", + .main_clk = "dss_sys_clk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, @@ -1620,7 +1619,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs), .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs), - .main_clk = "dss_fck", + .main_clk = "dss_48mhz_clk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, @@ -1706,7 +1705,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { .clkdm_name = "l3_dss_clkdm", .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs), - .main_clk = "dss_fck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, @@ -1775,7 +1773,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { .name = "dss_venc", .class = &omap44xx_venc_hwmod_class, .clkdm_name = "l3_dss_clkdm", - .main_clk = "dss_fck", + .main_clk = "dss_tv_clk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, @@ -1855,7 +1853,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { .clkdm_name = "l4_wkup_clkdm", .mpu_irqs = omap44xx_gpio1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), - .main_clk = "gpio1_ick", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, @@ -1911,7 +1908,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), - .main_clk = "gpio2_ick", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, @@ -1967,7 +1963,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), - .main_clk = "gpio3_ick", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, @@ -2023,7 +2018,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), - .main_clk = "gpio4_ick", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, @@ -2079,7 +2073,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio5_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), - .main_clk = "gpio5_ick", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, @@ -2135,7 +2128,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio6_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), - .main_clk = "gpio6_ick", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, @@ -2216,7 +2208,7 @@ static struct omap_hwmod omap44xx_hsi_hwmod = { .clkdm_name = "l3_init_clkdm", .mpu_irqs = omap44xx_hsi_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs), - .main_clk = "hsi_fck", + .main_clk = "hsi_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, @@ -2295,7 +2287,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), .sdma_reqs = omap44xx_i2c1_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), - .main_clk = "i2c1_fck", + .main_clk = "func_96m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, @@ -2351,7 +2343,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), .sdma_reqs = omap44xx_i2c2_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), - .main_clk = "i2c2_fck", + .main_clk = "func_96m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, @@ -2407,7 +2399,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), .sdma_reqs = omap44xx_i2c3_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), - .main_clk = "i2c3_fck", + .main_clk = "func_96m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, @@ -2463,7 +2455,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), .sdma_reqs = omap44xx_i2c4_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), - .main_clk = "i2c4_fck", + .main_clk = "func_96m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, @@ -2560,7 +2552,7 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs), .rst_lines = omap44xx_ipu_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), - .main_clk = "ipu_fck", + .main_clk = "ducati_clk_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, @@ -2649,7 +2641,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs), .sdma_reqs = omap44xx_iss_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs), - .main_clk = "iss_fck", + .main_clk = "ducati_clk_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, @@ -2764,7 +2756,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs), .rst_lines = omap44xx_iva_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), - .main_clk = "iva_fck", + .main_clk = "dpll_iva_m5x2_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, @@ -2837,7 +2829,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { .clkdm_name = "l4_wkup_clkdm", .mpu_irqs = omap44xx_kbd_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs), - .main_clk = "kbd_fck", + .main_clk = "sys_32k_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, @@ -2998,7 +2990,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs), .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs), - .main_clk = "mcbsp1_fck", + .main_clk = "func_mcbsp1_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, @@ -3074,7 +3066,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs), .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs), - .main_clk = "mcbsp2_fck", + .main_clk = "func_mcbsp2_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, @@ -3150,7 +3142,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs), .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs), - .main_clk = "mcbsp3_fck", + .main_clk = "func_mcbsp3_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, @@ -3205,7 +3197,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs), .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs), - .main_clk = "mcbsp4_fck", + .main_clk = "per_mcbsp4_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, @@ -3300,7 +3292,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs), .sdma_reqs = omap44xx_mcpdm_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs), - .main_clk = "mcpdm_fck", + .main_clk = "pad_clks_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, @@ -3388,7 +3380,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs), .sdma_reqs = omap44xx_mcspi1_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs), - .main_clk = "mcspi1_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, @@ -3451,7 +3443,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs), .sdma_reqs = omap44xx_mcspi2_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs), - .main_clk = "mcspi2_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, @@ -3514,7 +3506,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs), .sdma_reqs = omap44xx_mcspi3_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs), - .main_clk = "mcspi3_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, @@ -3575,7 +3567,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs), .sdma_reqs = omap44xx_mcspi4_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs), - .main_clk = "mcspi4_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, @@ -3663,7 +3655,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs), .sdma_reqs = omap44xx_mmc1_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs), - .main_clk = "mmc1_fck", + .main_clk = "hsmmc1_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, @@ -3726,7 +3718,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs), .sdma_reqs = omap44xx_mmc2_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs), - .main_clk = "mmc2_fck", + .main_clk = "hsmmc2_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, @@ -3783,7 +3775,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs), .sdma_reqs = omap44xx_mmc3_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs), - .main_clk = "mmc3_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, @@ -3838,7 +3830,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs), .sdma_reqs = omap44xx_mmc4_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs), - .main_clk = "mmc4_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, @@ -3893,7 +3885,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs), .sdma_reqs = omap44xx_mmc5_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs), - .main_clk = "mmc5_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, @@ -4009,7 +4001,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { .clkdm_name = "l4_ao_clkdm", .mpu_irqs = omap44xx_smartreflex_core_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), - .main_clk = "smartreflex_core_fck", + .main_clk = "l4_wkup_clk_mux_ck", .vdd_name = "core", .prcm = { .omap4 = { @@ -4058,7 +4050,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { .clkdm_name = "l4_ao_clkdm", .mpu_irqs = omap44xx_smartreflex_iva_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs), - .main_clk = "smartreflex_iva_fck", + .main_clk = "l4_wkup_clk_mux_ck", .vdd_name = "iva", .prcm = { .omap4 = { @@ -4107,7 +4099,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .clkdm_name = "l4_ao_clkdm", .mpu_irqs = omap44xx_smartreflex_mpu_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs), - .main_clk = "smartreflex_mpu_fck", + .main_clk = "l4_wkup_clk_mux_ck", .vdd_name = "mpu", .prcm = { .omap4 = { @@ -4257,7 +4249,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { .clkdm_name = "l4_wkup_clkdm", .mpu_irqs = omap44xx_timer1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs), - .main_clk = "timer1_fck", + .main_clk = "dmt1_clk_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, @@ -4305,7 +4297,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_timer2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs), - .main_clk = "timer2_fck", + .main_clk = "cm2_dm2_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, @@ -4353,7 +4345,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_timer3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs), - .main_clk = "timer3_fck", + .main_clk = "cm2_dm3_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, @@ -4401,7 +4393,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_timer4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs), - .main_clk = "timer4_fck", + .main_clk = "cm2_dm4_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, @@ -4468,7 +4460,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_timer5_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs), - .main_clk = "timer5_fck", + .main_clk = "timer5_sync_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, @@ -4535,7 +4527,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_timer6_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs), - .main_clk = "timer6_fck", + .main_clk = "timer6_sync_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, @@ -4602,7 +4594,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_timer7_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs), - .main_clk = "timer7_fck", + .main_clk = "timer7_sync_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, @@ -4669,7 +4661,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_timer8_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs), - .main_clk = "timer8_fck", + .main_clk = "timer8_sync_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, @@ -4717,7 +4709,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_timer9_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs), - .main_clk = "timer9_fck", + .main_clk = "cm2_dm9_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, @@ -4765,7 +4757,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_timer10_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs), - .main_clk = "timer10_fck", + .main_clk = "cm2_dm10_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, @@ -4813,7 +4805,7 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_timer11_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs), - .main_clk = "timer11_fck", + .main_clk = "cm2_dm11_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, @@ -4890,7 +4882,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), .sdma_reqs = omap44xx_uart1_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), - .main_clk = "uart1_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, @@ -4945,7 +4937,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), .sdma_reqs = omap44xx_uart2_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), - .main_clk = "uart2_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, @@ -5001,7 +4993,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), .sdma_reqs = omap44xx_uart3_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), - .main_clk = "uart3_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, @@ -5056,7 +5048,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), .sdma_reqs = omap44xx_uart4_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), - .main_clk = "uart4_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, @@ -5137,7 +5129,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .mpu_irqs = omap44xx_usb_otg_hs_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs), - .main_clk = "usb_otg_hs_ick", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, @@ -5212,7 +5203,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { .clkdm_name = "l4_wkup_clkdm", .mpu_irqs = omap44xx_wd_timer2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), - .main_clk = "wd_timer2_fck", + .main_clk = "sys_32k_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, @@ -5279,7 +5270,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_wd_timer3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), - .main_clk = "wd_timer3_fck", + .main_clk = "sys_32k_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,