diff mbox

[v2,5/5] OMAP4: powerdomain data: Remove unsupported MPU powerdomain state

Message ID 1309552060-4547-6-git-send-email-b-cousson@ti.com (mailing list archive)
State New, archived
Headers show

Commit Message

Benoit Cousson July 1, 2011, 8:27 p.m. UTC 
From: Santosh Shilimkar <santosh.shilimkar@ti.com>

On OMAP4430 devices, because of boot ROM code bug, MPU OFF state can't
be attempted independently. When coming out of MPU OFF state, ROM code
disables the clocks of IVAHD, TESLA which is not desirable. Hence the
MPU OFF state is not usable on OMAP4430 devices.

OMAP4460 onwards, MPU OFF state will be descoped completely because
the DDR firewall falls in MPU power domain. When the MPU hit OFF state,
DDR won't be accessible for other initiators. The deepest state supported
is open switch retention (OSWR) just like CORE and PER PD on OMAP4430.

So in summary MPU power domain OFF state is not supported on OMAP4
and onwards designs. Thanks to new PRCM design, device off mode can
still be achieved with power domains hitting OSWR state.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[b-cousson@ti.com: Fix changelog typos]
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/powerdomains44xx_data.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Comments

Paul Walmsley July 6, 2011, 5:29 a.m. UTC | #1 
On Fri, 1 Jul 2011, Benoit Cousson wrote:

> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
> 
> On OMAP4430 devices, because of boot ROM code bug, MPU OFF state can't
> be attempted independently. When coming out of MPU OFF state, ROM code
> disables the clocks of IVAHD, TESLA which is not desirable. Hence the
> MPU OFF state is not usable on OMAP4430 devices.
> 
> OMAP4460 onwards, MPU OFF state will be descoped completely because
> the DDR firewall falls in MPU power domain. When the MPU hit OFF state,
> DDR won't be accessible for other initiators. The deepest state supported
> is open switch retention (OSWR) just like CORE and PER PD on OMAP4430.
> 
> So in summary MPU power domain OFF state is not supported on OMAP4
> and onwards designs. Thanks to new PRCM design, device off mode can
> still be achieved with power domains hitting OSWR state.
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> [b-cousson@ti.com: Fix changelog typos]
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> Cc: Paul Walmsley <paul@pwsan.com>

Thanks, this patch has been queued for 3.1 at 
git://git.pwsan.com/linux-2.6 in the 'hardware_workarounds_3.1' branch.


- Paul
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diff mbox

Patch

diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 8f46e7d..247e794 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -205,7 +205,7 @@  static struct powerdomain mpu_44xx_pwrdm = {
 	.prcm_offs	  = OMAP4430_PRM_MPU_INST,
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts		  = PWRSTS_RET_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
 	.banks		  = 3,
 	.pwrsts_mem_ret	= {